Datasheet > A32400DX-1PQG240I

A32400DX-1PQG240I

更新时间： 2024-02-06 09:06:56

品牌	Logo	应用领域
ACTEL		栅可编程逻辑
页数	文件大小	规格书
22页	207K
描述
Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

A32400DX-1PQG240I 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	PLASTIC, QFP-240	Reach Compliance Code：	compliant
风险等级：	5.84	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G240	JESD-609代码：	e3
长度：	32 mm	湿度敏感等级：	3
可配置逻辑块数量：	2526	等效关口数量：	40000
端子数量：	240	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2526 CLBS, 40000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：	245	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	32 mm
Base Number Matches：	1

A32400DX-1PQG240I 数据手册

浏览型号A32400DX-1PQG240I的Datasheet PDF文件第3页

浏览型号A32400DX-1PQG240I的Datasheet PDF文件第4页

浏览型号A32400DX-1PQG240I的Datasheet PDF文件第5页

浏览型号A32400DX-1PQG240I的Datasheet PDF文件第7页

浏览型号A32400DX-1PQG240I的Datasheet PDF文件第8页

浏览型号A32400DX-1PQG240I的Datasheet PDF文件第9页

I/O Mo d u le s

segments. The minimum horizontal segment length is the

width of a module-pair, and the maximum horizontal

segment length is the full length of the channel. Any segment

that spans more than one-third the row length is considered a

long horizontal segment. A typical channel is shown in

Figure 6. Non-dedicated horizontal routing tracks are used to

route signal nets. Dedicated routing tracks are used for the

global clock networks and for power and ground tie-off

tracks.

The I/O modules provide the interface between the device

pins and the logic array (shown in Figure 5). A variety of I/O

configurations, determined by a library macro selection, can

be implemented in the module (refer to the Macro Library

Guide for more information). I/O modules contain input and

output latches as well as a tri-state buffer. These features

allow the module to be configured for input, output, or

bi-directional pins.

Vertical Routing

Other tracks run vertically through the module. Vertical

tracks are of three types: input, output, and long. Vertical

tracks are also divided into one or more segments. Each

segment in an input track is dedicated to the input of a

particular module. Each segment in an output track is

dedicated to the output of a particular module. Long segments

are uncommitted and can be assigned during routing. Each

output segment spans four channels (two above and two

below), except near the top and bottom of the array where

edge effects occur. An example of vertical routing tracks and

segments is shown in Figure 6.

PAD

From Array

G/CLK*

To Array

Segmented

Logic

G/CLK*

horizontal

Modules

routing

tracks

* Can be conﬁgured as a Latch or D Flip-Flop

(using C-module)

Figure 5 • I/O Module

Antifuses

I/O modules contain input and output latches for capturing

data prior to and/or from the device pins. In addition, the

Actel Designer Series software tools can build a D flip-flop

using a C-module in conjunction with the I/O latch to register

input and/or output signals. Actel’s Designer Series

development tools provide a design library of I/O macros

which can implement all I/O configurations supported by the

3200DX.

Vertical routing tracks

Figure 6 • Horizontal Routing Tracks and Segments

Antifuse Structures

R o u t in g S t r u c t u r e

An antifuse is a “normally open” structure as opposed to the

normally closed fuse structure used in PROMs or PALs. The

use of antifuses to implement a Programmable Logic Device

results in highly testable structures as well as efficient

programming algorithms. The structure is highly testable

because there are no pre-existing connections; therefore,

temporary connections can be made using pass transistors.

These temporary connections can isolate individual antifuses

to be programmed as well as isolate individual circuit

structures to be tested. This can be done both before and after

programming. For example, all metal tracks can be tested for

continuity and shorts between adjacent tracks, and the

functionality of all logic modules can be verified.

The 3200DX architecture uses Horizontal and Vertical

routing tracks to interconnect the various logic and I/O

modules. These routing tracks are metal interconnects that

may either be of continuous length or broken into pieces

called segments. Varying segment lengths allows the

interconnect of over 90% of design tracks to occur with only

two antifuse connections. Segments can be joined together at

the ends, using antifuses, to increase their lengths up to the

full length of the track. All interconnects can be

accomplished with a maximum of four antifuses.

Horizontal Routing

Horizontal channels are located between the rows of modules

and are composed of several routing tracks. The horizontal

routing tracks within the channel are divided into one or more

1...3 4 567 8 9...22

下载PDF

与A32400DX-1PQG240I相关器件

型号	品牌	描述	获取价格	数据表
A32400DX-1RQ240C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-1RQ240I	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-2BGG313I	ACTEL	Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PBGA313, BGA-313	获取价格
A32400DX-2PQG240C	ACTEL	Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240	获取价格
A32400DX-2RQ240C	ETC	Field Programmable Gate Array (FPGA)	获取价格
A32400DX-2RQ240I	ETC	Field Programmable Gate Array (FPGA)	获取价格

与A32400DX-1PQG240I相关文章

VIPER22A的资料手册解读、引脚参数说明、代换型号推荐
2024-05-14

6
ADS1256的资料手册解读、采集电压范围、读数变化原因分析及实际测量遇到的问题
2024-05-14

8
MAX6675资料手册参数详解、引脚配置说明
2024-05-13

13
LM258引脚图及功能介绍、主要参数分析
2024-05-13

11

产品中心

服务支持

精选活动

关于我们

帮助中心

A32400DX-1PQG240I

A32400DX-1PQG240I 技术参数

A32400DX-1PQG240I 数据手册

与A32400DX-1PQG240I相关器件

与A32400DX-1PQG240I相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

A32400DX-1PQG240I

A32400DX-1PQG240I 技术参数

A32400DX-1PQG240I 数据手册

与A32400DX-1PQG240I相关器件

与A32400DX-1PQG240I相关文章

您还可以找

您在本页遇到什么问题？