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A32400DX-1PQG240I PDF预览

A32400DX-1PQG240I

更新时间: 2024-02-04 18:20:49
品牌 Logo 应用领域
ACTEL 可编程逻辑
页数 文件大小 规格书
22页 207K
描述
Field Programmable Gate Array, 2526 CLBs, 40000 Gates, CMOS, PQFP240, PLASTIC, QFP-240

A32400DX-1PQG240I 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:PLASTIC, QFP-240Reach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
JESD-30 代码:S-PQFP-G240JESD-609代码:e3
长度:32 mm湿度敏感等级:3
可配置逻辑块数量:2526等效关口数量:40000
端子数量:240最高工作温度:85 °C
最低工作温度:-40 °C组织:2526 CLBS, 40000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
峰值回流温度(摄氏度):245可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:4.1 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:32 mm
Base Number Matches:1

A32400DX-1PQG240I 数据手册

 浏览型号A32400DX-1PQG240I的Datasheet PDF文件第1页浏览型号A32400DX-1PQG240I的Datasheet PDF文件第3页浏览型号A32400DX-1PQG240I的Datasheet PDF文件第4页浏览型号A32400DX-1PQG240I的Datasheet PDF文件第5页浏览型号A32400DX-1PQG240I的Datasheet PDF文件第6页浏览型号A32400DX-1PQG240I的Datasheet PDF文件第7页 
timing analysis, user programming, and debug and diagnostic  
probe capabilities. In addition, Designer 3.0 provides the  
DirectTime™ tool which provides deterministic as well as  
controllable timing. DirectTime allows the designer to  
specify the performance requirements of individual paths and  
system clock(s). Using these specifications, the software will  
automatically optimize the placement and routing of the logic  
to meet these constraints. Included with Designer 3.0 is  
provides CAE interfaces to Cadence, Escalade, Exemplar  
Logic, IST, Mentor Graphics‚ OrCAD, Synopsys, and  
Viewlogic design environments. Additional development  
tools are supported through Actel’s Industry Alliance  
Program, including DATA I/O (ABEL FPGA) and MINC.  
Actel’s FPGAs are an ideal solution for shortening the system  
design and development cycle and offers a cost-effective  
alternative for low volume production runs. The 3200DX  
devices are an excellent choice for integrating logic that is  
currently implemented in TTL, PALs, CPLDs and FPGAs.  
Some example applications include high-speed controllers  
and address decoding, peripheral bus interfaces, DSP, and  
co-processor functions.  
Actel’s ACTgen Macro Builder. ACTgen allows the  
designer to quickly build fast, efficient logic functions such  
as counters, adders, FIFOs, and RAM.  
The Designer Series tools provide designers the capability to  
move up to High-Level Description Languages, such as  
VHDL and Verilog, or use schematic design entry with  
interfaces to most EDA tools. Designer Series 3.0 is  
supported on the following development platforms: 386/486  
and Pentium PC, Sun‚ and HP‚ workstations. The software  
D e v i c e R e s o u r c e s  
User I/Os  
PLCC  
84-pin  
PQFP  
160-pin  
PQFP  
208-pin  
PQFP  
240-pin  
TQFP  
176-pin  
BGA  
225-pin  
BGA  
313-pin  
Device Series  
A3265DX  
72  
72  
125  
125  
125  
156  
176  
176  
126  
151  
151  
156  
176  
TBD  
A32100DX  
A32140DX  
A32200DX  
A32300DX  
A32400DX  
TBD  
TBD  
TBD  
206  
254  
TBD  
Package Definitions (Consult your local Actel Sales Representative for product availability.)  
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array  
O r d e r i n g I n f o r m a t i o n  
A32200  
DX –  
1
PQ  
208  
C
Application (Temperature Range)  
C = Commercial (0 to +70°C)  
I
= Industrial (–40 to +85°C)  
PP = Pre-Production  
Package Lead Count  
Package Type  
PL = Plastic J-Leaded Chip Carrier  
PQ = Plastic Quad Flatpack  
TQ = Thin (1.4 mm) Quad Flatpack  
RQ = Power Quad Flatpack  
BG = Ball Grid Array  
Speed Grade  
Blank = Standard Speed  
–1 = Approximately 15% faster than Standard  
–2 = Approximately 25% faster than Standard  
Sub Family  
Part Number  
2

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