A28F200BX-T/B
2-MBIT (128K x 16, 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
Automotive
Y
Y
Y
x8/x16 Input/Output Architecture
Very High-Performance Read
Ð 90 ns Maximum Access Time
Ð 45 ns Maximum Output Enable Time
Ð A28F200BX-T, A28F200BX-B
Ð For High Performance and High
Integration 16-bit and 32-bit CPUs
Y
Y
Y
Low Power Consumption
Ð 25 mA Typical Active Read Current
Optimized High Density Blocked
Architecture
Ð One 16 KB Protected Boot Block
Ð Two 8 KB Parameter Blocks
Ð One 96 KB Main Block
Deep Power-Down/Reset Input
Ð Acts as Reset for Boot Operations
Automotive Temperature Operation
b
a
40 C to 125 C
Ð
§
§
Write Protection for Boot Block
Ð One 128 KB Main Block
Ð Top or Bottom Boot Locations
Y
Y
Y
Y
Extended Cycling Capability
Ð 1,000 Block Erase Cycles
Industry Standard Surface Mount
Packaging
Ð JEDEC ROM Compatible
44-Lead PSOP
Automated Word/Byte Write and
Block Erase
Ð Command User Interface
Ð Status Register
Ð Erase Suspend Capability
Y
Y
Y
12V Word/Byte Write and Block Erase
e
g
12V 5% Standard
Ð V
PP
ETOXTM III Flash Technology
Ð 5V Read
Y
Y
SRAM-Compatible Write Interface
Automatic Power Savings Feature
Independent Software Vendor Support
Ð 1 mA Typical I
CC
Static Operation
Active Current in
Y
Hardware Data Protection Feature
Ð Erase/Write Lockout during Power
Transitions
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copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
©
COPYRIGHT INTEL CORPORATION, 1995
November 1995
Order Number: 290500-003