Datasheet > A1280A-1CQG172E

A1280A-1CQG172E

更新时间： 2024-09-18 03:30:31

品牌	Logo	应用领域
ACTEL		时钟栅可编程逻辑
页数	文件大小	规格书
98页	2005K
描述
Field Programmable Gate Array, 1232 CLBs, 8000 Gates, 60MHz, CMOS, CQFP172, CAVITY-UP, CERAMIC, QFP-172

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A1280A-1CQG172E 数据手册

v3.0

HiRel FPGAs

Features

• Low-Power 0.8µ CMOS Technology

• Highly Predictable Performance with 100% Automatic

Placement and Routing

3200DX Features

• 100 MHz System Logic Integration

• Device Sizes from 1,200 to 20,000 Gates

• Up to 6 Fast, Low-Skew Clock Networks

• Up to 202 User-Programmable I/O Pins

• More Than 500 Macro Functions

• Up to 1,276 Dedicated Flip-Flops

• I/O Drive to 10 mA

• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable

Dual-Port SRAM

• Fast Wide-Decode Circuitry

• Low-Power 0.6µ CMOS Technology

1200XL Features

• Pin for Pin Compatible with ACT 2

• System Performance to 50 MHz over Military Temperature

• Low-Power 0.6µ CMOS Technology

• Devices Available to DSCC SMD

• CQFP and CPGA Packaging

• Nonvolatile, User Programmable

• Logic Fully Tested Prior to Shipment

• 100% Military Temperature Tested (–55°C to +125°C)

• QML Certified Devices

ACT 2 Features

• Best-Value, High-Capacity FPGA Family

• System Performance to 40 MHz over Military Temperature

• Low-Power 1.0µ CMOS Technology

• Proven Reliability Data Available

• Successful Military/Avionics Supplier for Over 10 Years

ACT 1 Features

ACT 3 Features

• Lowest-Cost FPGA Family

• Highest-Performance, Highest-Capacity FPGA Family

• System Performance to 60 MHz over Military Temperature

• System Performance to 20 MHz over Military Temperature

• Low-Power 1.0µ CMOS Technology

Product Family Profile (more devices on page 2)

Family

Device

3200DX

ACT 3

1200XL

A32100DX A32200DX

A1425A

A1460A

A14100A

A1280XL

Capacity

System Gates

Logic Gates

SRAM Bits

15,000

10,000

2,048

30,000

20,000

2,560

3,750

2,500

9,000

6,000

15,000

10,000

12,000

8,000

Logic Modules

S-Modules

C-Modules

Decode

1,362

700

662

2,414

1,230

1,184

310

160

150

848

432

416

1,377

697

680

1,232

624

608

Flip-Flops (Maximum)

User I/Os (Maximum)

738

152

1,276

202

435

100

976

168

1,493

228

998

140

Performance

System Speed (maximum)

55 MHz

60 MHz

50 MHz

Packages (by Pin Count)

CPGA

CQFP

133

132

207

196

257

256

176

172

208, 256

January 2000

12 3 4 5 6 7...98

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