Datasheet > A1010B-1PL68C

A1010B-1PL68C

更新时间： 2024-11-11 20:44:11

品牌	Logo	应用领域
美高森美 - MICROSEMI		时钟栅可编程逻辑
页数	文件大小	规格书
24页	159K
描述
Field Programmable Gate Array, 547 CLBs, 2000 Gates, 53MHz, 295-Cell, CMOS, PQCC68, PLASTIC, LCC-68

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技术参数
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A1010B-1PL68C 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	PLASTIC, LCC-68
针数：	68	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.84
Is Samacsys：	N	其他特性：	MAX 57 I/OS
最大时钟频率：	53 MHz	CLB-Max的组合延迟：	3.8 ns
JESD-30 代码：	S-PQCC-J68	JESD-609代码：	e0
长度：	24.2316 mm	湿度敏感等级：	3
可配置逻辑块数量：	547	等效关口数量：	2000
输入次数：	57	逻辑单元数量：	295
输出次数：	57	端子数量：	68
最高工作温度：	70 °C	最低工作温度：
组织：	547 CLBS, 2000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC68,1.0SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	225	电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	24.2316 mm
Base Number Matches：	1

A1010B-1PL68C 数据手册

ACT^™1 Series FPGAs

F e a t u r e s

A security fuse may be programmed to disable all further

programming and to protect the design from being copied or

reverse engineered.

• 5V and 3.3V Families fully compatible with JEDEC

specifications

• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)

• Replaces up to 50 TTL Packages

• Replaces up to twenty 20-Pin PAL^®Packages

P r o d u c t F a m i l y P r o f i l e

A1010B

A1020B

Device

A10V10B A10V20B

• Design Library with over 250 Macro Functions

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages

20-Pin PAL Equivalent Packages

1,200

3,000

2,000

6,000

• Gate Array Architecture Allows Completely Automatic

Place and Route

• Up to 547 Programmable Logic Modules

• Up to 273 Flip-Flops

Logic Modules

295

147

547

273

Flip-Flops (maximum)

• Data Rates to 75 MHz

Routing Resources

• Two In-Circuit Diagnostic Probe Pins Support Speed

Analysis to 25 MHz

Horizontal Tracks/Channel

Vertical Tracks/Column

PLICE Antifuse Elements

• Built-In High Speed Clock Distribution Network

• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)

• Nonvolatile, User Programmable

112,000

186,000

User I/Os (maximum)

Packages:

44 PLCC 44 PLCC

68 PLCC 68 PLCC

84 PLCC

• Fabricated in 1.0 micron CMOS technology

100 PQFP 100 PQFP

80 VQFP 80 VQFP

84 CPGA 84 CPGA

84 CQFP

D e s c r i p t i o n

The ACT™ 1 Series of field programmable gate arrays

(FPGAs) offers a variety of package, speed, and application

combinations. Devices are implemented in silicon gate,

1-micron two-level metal CMOS, and they employ Actel’s

PLICE^®antifuse technology. The unique architecture offers

gate array flexibility, high performance, and instant

turnaround through user programming. Device utilization is

typically 95 to 100 percent of available logic modules.

Performance

5 V Data Rate (maximum)

3.3 V Data Rate (maximum)

75 MHz

55 MHz

75 MHz

55 MHz

Note: See Product Plan on page 1-286 for package availability.

T h e D e s i g n e r a n d D e s i g n e r

A d v a n t a g e ™ S y s t e m s

ACT 1 devices also provide system designers with unique

on-chip diagnostic probe capabilities, allowing convenient

testing and debugging. Additional features include an on-chip

clock driver with a hardwired distribution network. The

network provides efficient clock distribution with minimum

skew.

The ACT 1 device family is supported by Actel’s Designer and

Designer Advantage Systems, allowing logic design

implementation with minimum effort. The systems offer

Microsoft^®Windows^™and X Windows^™graphical user

interfaces and integrate with the resident CAE system to

provide a complete gate array design environment: schematic

capture, simulation, fully automatic place and route, timing

verification, and device programming. The systems also

include the ACTmap^™VHDL optimization and synthesis tool

and the ACTgen^™Macro Builder, a powerful macro function

generator for counters, adders, and other structural blocks.

The user-definable I/Os are capable of driving at both TTL

and CMOS drive levels. Available packages include plastic

and ceramic J-leaded chip carriers, ceramic and plastic quad

flatpacks, and ceramic pin grid array.

A p r i l 1 9 9 6

1 -2 8 3

12 3 4 5 6 7...24

中文翻译

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A1010B-1PL68C 替代型号

型号	品牌	替代类型	描述	数据表
A1010B-PL68C	MICROSEMI	完全替代	Field Programmable Gate Array, 547 CLBs, 2000 Gates, 45MHz, 295-Cell, CMOS, PQCC68, PLASTI
A1010B-2PLG68C	MICROSEMI	完全替代	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 60MHz, 295-Cell, CMOS, PQCC68, PLASTI

与A1010B-1PL68C相关器件

型号	品牌	获取价格	描述	数据表
A1010B-1PL68I	ACTEL	获取价格	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQCC68, PLAS
A1010B-1PL68I	MICROSEMI	获取价格	暂无描述
A1010B-1PL84B	ACTEL	获取价格	ACT 1 Series FPGAs
A1010B-1PL84C	ACTEL	获取价格	ACT 1 Series FPGAs
A1010B-1PL84I	ACTEL	获取价格	ACT 1 Series FPGAs
A1010B-1PL84M	ACTEL	获取价格	ACT 1 Series FPGAs
A1010B-1PLG44C	ACTEL	获取价格	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 53MHz, 295-Cell, CMOS, PQCC44, PLASTI
A1010B-1PLG44I	ACTEL	获取价格	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQCC44, PLAS
A1010B-1PLG68C	MICROSEMI	获取价格	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 53MHz, 295-Cell, CMOS, PQCC68, PLASTI
A1010B-1PLG68I	MICROSEMI	获取价格	Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQCC68, PLAS

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