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A1010B-1PLG68C

更新时间： 2024-11-11 20:11:03
品牌 Logo 应用领域
美高森美 - MICROSEMI 栅
页数 文件大小 规格书
24页 166K
描述
Field Programmable Gate Array, 295 CLBs, 1200 Gates, 53MHz, 295-Cell, CMOS, PQCC68, PLASTIC, MS-007-AD, LCC-68

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A1010B-1PLG68C 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：PLASTIC, MS-007-AD, LCC-68Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：8.59
其他特性：MAX 57 I/OS最大时钟频率：53 MHz
CLB-Max的组合延迟：3.8 nsJESD-30 代码：S-PQCC-J68
JESD-609代码：e3长度：24.13 mm
湿度敏感等级：3可配置逻辑块数量：295
等效关口数量：1200端子数量：68
最高工作温度：70 °C最低工作温度：
组织：295 CLBS, 1200 GATES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：245
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：4.445 mm最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：24.13 mmBase Number Matches：1

A1010B-1PLG68C 数据手册

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ACT™ 1 Series FPGAs  
F e a t u r e s  
A security fuse may be programmed to disable all further  
programming and to protect the design from being copied or  
reverse engineered.  
• 5V and 3.3V Families fully compatible with JEDEC  
specifications  
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)  
• Replaces up to 50 TTL Packages  
• Replaces up to twenty 20-Pin PAL® Packages  
P r o d u c t F a m i l y P r o f i l e  
A1010B  
A1020B  
Device  
A10V10B A10V20B  
• Design Library with over 250 Macro Functions  
Capacity  
Gate Array Equivalent Gates  
PLD Equivalent Gates  
TTL Equivalent Packages  
20-Pin PAL Equivalent Packages  
1,200  
3,000  
30  
2,000  
6,000  
50  
• Gate Array Architecture Allows Completely Automatic  
Place and Route  
12  
20  
• Up to 547 Programmable Logic Modules  
• Up to 273 Flip-Flops  
Logic Modules  
295  
147  
547  
273  
Flip-Flops (maximum)  
• Data Rates to 75 MHz  
Routing Resources  
• Two In-Circuit Diagnostic Probe Pins Support Speed  
Analysis to 25 MHz  
Horizontal Tracks/Channel  
Vertical Tracks/Column  
PLICE Antifuse Elements  
22  
13  
22  
13  
• Built-In High Speed Clock Distribution Network  
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)  
• Nonvolatile, User Programmable  
112,000  
186,000  
User I/Os (maximum)  
Packages:  
57  
69  
44 PLCC 44 PLCC  
68 PLCC 68 PLCC  
84 PLCC  
• Fabricated in 1.0 micron CMOS technology  
100 PQFP 100 PQFP  
80 VQFP 80 VQFP  
84 CPGA 84 CPGA  
84 CQFP  
D e s c r i p t i o n  
The ACT™ 1 Series of field programmable gate arrays  
(FPGAs) offers a variety of package, speed, and application  
combinations. Devices are implemented in silicon gate,  
1-micron two-level metal CMOS, and they employ Actel’s  
PLICE® antifuse technology. The unique architecture offers  
gate array flexibility, high performance, and instant  
turnaround through user programming. Device utilization is  
typically 95 to 100 percent of available logic modules.  
Performance  
5 V Data Rate (maximum)  
3.3 V Data Rate (maximum)  
75 MHz  
55 MHz  
75 MHz  
55 MHz  
Note: See Product Plan on page 1-286 for package availability.  
T h e D e s i g n e r a n d D e s i g n e r  
A d v a n t a g e ™ S y s t e m s  
ACT 1 devices also provide system designers with unique  
on-chip diagnostic probe capabilities, allowing convenient  
testing and debugging. Additional features include an on-chip  
clock driver with a hardwired distribution network. The  
network provides efficient clock distribution with minimum  
skew.  
The ACT 1 device family is supported by Actel’s Designer and  
Designer Advantage Systems, allowing logic design  
implementation with minimum effort. The systems offer  
Microsoft® Windows™ and X Windows™ graphical user  
interfaces and integrate with the resident CAE system to  
provide a complete gate array design environment: schematic  
capture, simulation, fully automatic place and route, timing  
verification, and device programming. The systems also  
include the ACTmap™ VHDL optimization and synthesis tool  
and the ACTgen™ Macro Builder, a powerful macro function  
generator for counters, adders, and other structural blocks.  
The user-definable I/Os are capable of driving at both TTL  
and CMOS drive levels. Available packages include plastic  
and ceramic J-leaded chip carriers, ceramic and plastic quad  
flatpacks, and ceramic pin grid array.  
A p r i l 1 9 9 6  
1 -2 8 3  
© 1996 Actel Corporation  
1234567...24

中文翻译

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A1010B-1PLG68C 替代型号

型号 品牌 替代类型 描述 数据表
A1010B-1PL68C MICROSEMI

完全替代

 Field Programmable Gate Array, 547 CLBs, 2000 Gates, 53MHz, 295-Cell, CMOS, PQCC68, PLASTI
A1010B-1PLG68I MICROSEMI

完全替代

 Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQCC68, PLAS
A40MX02-1PLG68 MICROSEMI

完全替代

 Field Programmable Gate Array, 295 CLBs, 3000 Gates, 92MHz, CMOS, PQCC68, ROHS COMPLIANT,

与A1010B-1PLG68C相关器件

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A1010B-1PLG68I MICROSEMI

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 		Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQCC68, PLAS
A1010B-1PQ100C ACTEL

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 		Field Programmable Gate Array, 295 CLBs, 1200 Gates, 53MHz, 295-Cell, CMOS, PQFP100, PLAST
A1010B-1PQ100C MICROSEMI

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 		Field Programmable Gate Array, 547 CLBs, 2000 Gates, 53MHz, 295-Cell, CMOS, PQFP100, PLAST
A1010B-1PQ100I ACTEL

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 		Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQFP100, PLA
A1010B-1PQ84B ACTEL

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 		ACT 1 Series FPGAs
A1010B-1PQ84C ACTEL

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 		ACT 1 Series FPGAs
A1010B-1PQ84I ACTEL

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 		ACT 1 Series FPGAs
A1010B-1PQ84M ACTEL

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 		ACT 1 Series FPGAs
A1010B-1PQG100C ACTEL

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 		Field Programmable Gate Array, 295 CLBs, 1200 Gates, 53MHz, 295-Cell, CMOS, PQFP100, PLAST
A1010B-1PQG100I ACTEL

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 		Field Programmable Gate Array, 295 CLBs, 1200 Gates, 47.7MHz, 295-Cell, CMOS, PQFP100, PLA

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