5秒后页面跳转
捷配首页

Datasheet > 9ZXL1950BKLF
9ZXL1950BKLF PDF预览

9ZXL1950BKLF

更新时间： 2024-09-18 01:07:59
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 296K
描述
19-output DB1900Z Low-Power Derivative w/85ohm Terminations

阅读下载

中文翻译

获取价格

9ZXL1950BKLF 数据手册

 浏览型号9ZXL1950BKLF的Datasheet PDF文件第4页浏览型号9ZXL1950BKLF的Datasheet PDF文件第5页浏览型号9ZXL1950BKLF的Datasheet PDF文件第6页浏览型号9ZXL1950BKLF的Datasheet PDF文件第8页浏览型号9ZXL1950BKLF的Datasheet PDF文件第9页浏览型号9ZXL1950BKLF的Datasheet PDF文件第10页 
9ZXL1950 DATASHEET  
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
Trf  
CONDITIONS  
MIN  
1.5  
TYP MAX UNITS NOTES  
V/ns  
%
Slew rate  
Slew rate matching  
Scope averaging on  
Slew rate matching.  
2.7  
8.8  
4
20  
1, 2, 3  
1, 2, 4  
∆
Trf  
Statistical measurement on single-ended signal  
using oscilloscope math function. (Scope  
averaging on)  
Voltage High  
Voltage Low  
VHigh  
VLow  
660  
787  
33  
850  
mV  
-150  
150  
Max Voltage  
Min Voltage  
Crossing Voltage (abs)  
Crossing Voltage (var)  
Vmax  
Vmin  
Vcross_abs  
Single ended signal using absolute value.  
Includes 300mV of over/undershoot. (Scope  
845  
9
471  
14  
1150  
mV  
-300  
250  
Scope averaging off  
Scope averaging off  
550  
140  
mV  
mV  
1, 5  
1, 6  
∆
-Vcross  
1
Ω
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with Zo = 85 differential trace impedance.  
2 Measured from differential waveform  
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around  
differential 0V.  
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on  
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the  
oscilloscope is to use for the edge rate calculations.  
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising  
edge (i.e. Clock rising and Clock# falling).  
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross  
∆
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.  
Clock Periods–Differential Outputs with Spread Spectrum Disabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC OFF  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
100.00  
133.33  
9.94900  
7.44925  
9.99900  
7.49925  
10.00000  
7.50000  
10.00100  
7.50075  
10.05100  
7.55075  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Clock Periods–Differential Outputs with Spread Spectrum Enabled  
Measurement Window  
1 Clock  
1us  
-SSC  
0.1s  
- ppm  
0.1s  
0.1s  
+ ppm  
Long-Term  
Average  
Max  
1us  
+SSC  
Short-Term  
Average  
Max  
1 Clock  
Center  
Freq.  
MHz  
SSC ON  
-c2c jitter  
AbsPer  
Min  
0 ppm  
Period  
Nominal  
+c2c jitter Units Notes  
AbsPer  
Max  
Short-Term Long-Term  
Average  
Min  
Average  
Min  
99.75  
133.00  
9.94906  
7.44930  
9.99906  
7.49930  
10.02406  
7.51805  
10.02506  
7.51880  
10.02607  
7.51955  
10.05107  
7.53830  
10.10107  
7.58830  
ns  
ns  
1,2,3  
1,2,4  
DIF  
Notes:  
1 Guaranteed by design and characterization, not 100% tested in production.  
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+  
accuracy requirements (+/-100ppm). The 9ZXL1950 itself does not contribute to ppm error.  
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode  
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode  
REVISION E 11/20/15  
7
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS  
1...45678910...18

中文翻译

下载PDF

与9ZXL1950BKLF相关器件

型号 品牌 获取价格 描述 数据表
9ZXL1950BKLFT IDT

获取价格

 		19-output DB1900Z Low-Power Derivative w/85ohm Terminations
9ZXL1950D RENESAS

获取价格

 		19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer
9ZXL1950DKILF IDT

获取价格

 		19-Output DB1900Z Derivative for PCIe Gen1–
9ZXL1950DKILFT IDT

获取价格

 		19-Output DB1900Z Derivative for PCIe Gen1–
9ZXL1951D IDT

获取价格

 		19-Output DB1900ZL Derivat ive for PCIe Gen1â
9ZXL1951D RENESAS

获取价格

 		19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer
9ZXL1951DNHGI IDT

获取价格

 		19-Output DB1900ZL Derivat ive for PCIe Gen1â
9ZXL1951DNHGI8 IDT

获取价格

 		19-Output DB1900ZL Derivat ive for PCIe Gen1â
A TTELEC

获取价格

 		Multi-Turn Precision Pot
A.01.C.301111 TAOGLAS

获取价格

 		Two Stage 30dB Active GPS Antenna

与9ZXL1950BKLF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证