9ZXL0832E / 9ZXL0852E Datasheet
Electrical Characteristics–Input/Supply/Common Output Parameters
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Symbol
VDDx
VDDIO
Parameter
Supply Voltage
Output Supply Voltage
Ambient Operating
Temperature
Conditions
Supply voltage for core and analog
Supply voltage for DIF outputs, if present
Minimum Typical Maximum
Units Notes
V
V
3.135
0.9975
3.3
1.05
3.465
3.465
TAMB
Industrial range (TIND
)
-40
25
85
°C
VIH
VIL
VIH
VIL
VIL
IIN
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
Single-ended inputs, except SMBus, tri-level inputs
2
VDD + 0.3
0.8
V
V
Single-ended inputs, except SMBus, tri-level inputs GND - 0.3
Tri-level inputs
Tri-level inputs
Tri-level inputs
2.2
1.2
VDD + 0.3
1.8
V
VDD/2
V
GND - 0.3
-5
0.8
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
5
μA
Input Current
VIN = 0 V; inputs with internal pull-up resistors
IINP
-50
50
μA
VIN = VDD; inputs with internal pull-down resistors
VDD = 3.3 V, Bypass Mode
Fibyp
Fipll
1
400
102.5
135
7
MHz
MHz
MHz
Input Frequency
Pin Inductance
Capacitance
VDD = 3.3 V, 100MHz PLL Mode
98.5
132
100.00
133.33
Fipll
VDD = 3.3 V, 133.33MHz PLL Mode
Lpin
nH
pF
pF
pF
1
1
CIN
Logic inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
5
CINDIF_IN
COUT
2.7
6
1,4
1
Output pin capacitance
From VDD power-up and after input clock stabilization
TSTAB
Clk Stabilization
1.0
1.8
ms
1,2
or de-assertion of PD# to 1st clock
Allowable frequency for PCIe applications
(Triangular modulation)
Input SS Modulation
Frequency PCIe
fMODINPCIe
tLATOE#
tDRVPD
30
4
33
10
kHz
clocks
μs
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
5
1,2,3
1,3
49
300
PD# de-assertion
tF
Tfall
Fall time of control inputs
5
5
ns
ns
2
2
tR
Trise
Rise time of control inputs
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200mV.
4 DIF_IN input.
©2018 Integrated Device Technology, Inc
6
August 14, 2018