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9ZXL0832EKILFT

更新时间： 2022-02-26 10:34:30
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
18页 274K
描述
8-Output DB800ZL Derivative PCIe Gen1–4 and UPI

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9ZXL0832EKILFT 数据手册

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9ZXL0832E / 9ZXL0852E Datasheet  
Pin Descriptions  
Pin #  
Pin Name  
^CKPWRGD_PD#  
GND  
Type  
IN  
Description  
Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent  
high assertions exit Power Down Mode. This pin has internal pull-up resistor.  
Ground pin.  
1
2
3
GND  
PWR  
Power supply for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered  
appropriately. Nominally 3.3V.  
VDDR  
4
5
6
7
DIF_IN  
IN  
IN  
HCSL true input.  
DIF_IN#  
SMBDAT  
SMBCLK  
HCSL complementary input.  
I/O  
IN  
Data pin of SMBUS circuitry  
Clock pin of SMBUS circuitry  
Complementary half of differential feedback output. This pin should NOT be connected to anything outside the chip. It exists to  
provide delay path matching to get 0 propagation delay.  
True half of differential feedback output. This pin should NOT be connected to anything outside the chip. It ex ists to provide delay  
path matching to get 0 propagation delay.  
8
9
FBOUT_NC#  
FBOUT_NC  
OUT  
OUT  
PWR  
IN  
10 VDD  
Power supply, nominally 3.3V.  
Active low input for enabling output 0. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
11 vOE0#  
12 NC  
N/A  
No connection.  
13 DIF0  
14 DIF0#  
15 VDD  
16 DIF1  
17 DIF1#  
OUT  
OUT  
PWR  
OUT  
OUT  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
Differential true clock output.  
Differential complementary clock output.  
Active low input for enabling output 1. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
18 vOE1#  
IN  
19 VDD  
20 NC  
PWR  
N/A  
Power supply, nominally 3.3V.  
No connection.  
21 DIF2  
22 DIF2#  
OUT  
OUT  
Differential true clock output.  
Differential complementary clock output.  
Active low input for enabling output 2. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
23 vOE2#  
24 vOE3#  
IN  
IN  
Active low input for enabling output 3. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
25 DIF3  
26 DIF3#  
27 VDD  
28 DIF4  
29 DIF4#  
OUT  
OUT  
PWR  
OUT  
OUT  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
Differential true clock output.  
Differential complementary clock output.  
Active low input for enabling output 4. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
30 vOE4#  
31 vOE5#  
IN  
IN  
Active low input for enabling output 5. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
32 DIF5  
33 DIF5#  
34 VDD  
35 DIF6  
36 DIF6#  
OUT  
OUT  
PWR  
OUT  
OUT  
Differential true clock output.  
Differential complementary clock output.  
Power supply, nominally 3.3V.  
Differential true clock output.  
Differential complementary clock output.  
Active low input for enabling output 6. This pin has an internal pull-down.  
1 = disable outputs, 0 = enable outputs.  
37 vOE6#  
38 VDD  
IN  
PWR  
Power supply, nominally 3.3V.  
©2018 Integrated Device Technology, Inc  
3
August 14, 2018  
1234567...18

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