Datasheet > 9ZXL0832E

9ZXL0832E

更新时间： 2022-02-26 10:34:30

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
18页	274K
描述
8-Output DB800ZL Derivative PCIe Gen1â4 and UPI

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数据手册

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9ZXL0832E 数据手册

9ZXL0832E / 9ZXL0852E Datasheet

Pin Descriptions (cont.)

Pin #

39 DIF7

Pin Name

Type

OUT

Description

Differential true clock output.

40 DIF7#

Differential complementary clock output.

Active low input for enabling output 7. This pin has an internal 120kohm pull-down.

1 = disable outputs, 0 = enable outputs.

Power supply, nominally 3.3V.

41 vOE7#

42 VDD

43 NC

PWR

N/A

No connection.

44 VDDA

45 NC

PWR

N/A

Power supply for PLL core.

No connection.

This pin prevents SMBus writes when asserted. SMBus reads are not affected. This pin has an internal 120kohm pull down.

0 = SMBus writes allows, 1 = SMBus writes blocked.

46 vSMB_WRTLOCK

LATCHED

47 ^100M_133M#

3.3V Input to select operating frequency. This pin has an internal 120kohm pull-up resistor. See Functionality Table for definition.

LATCHED Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kohm pull up resistor. See PLL Operating

48 ^HIBW_BYPM_LOBW#

Mode Table for details.

Ground

PWR

EPAD

Test Loads

Low-Power HCSL Output Test Load

(standard PCIe source-terminated test load)

C_L

Test

Points

Differential Zo

C_L

Parameters for Low -Pow er HCSL Output Test Load

Device

Rs (Ω)

Internal

7.5

Zo (Ω) L (Inches) CL (pF)

100

9ZXL083x

9ZXL085x*

100

*Contact factory for versions of this device with Zo=100Ω.

Alternate Terminations

The LP-HCSL output can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's

“Universal” Low-Power HCSL Outputs” for termination schemes for LVPECL, LVDS, CML and SSTL.

August 14, 2018

1 2 345 6 7...18

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