Datasheet > 9ZX21201

9ZX21201

更新时间： 2023-12-20 18:45:29

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
17页	515K
描述
12-output DB1200Z Compliant Buffer

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9ZX21201 数据手册

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

Pin Description (continued)

GND

DIF_4

DIF_4#

PWR Ground pin.

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

Active low input for enabling DIF pair 4

1 =disable outputs, 0 = enable outputs

Active low input for enabling DIF pair 5. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

vOE4#

vOE5#

DIF_5

DIF_5#

VDD

GND

DIF_6

DIF_6#

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

PWR Power supply, nominal 3.3V

PWR Ground pin.

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

Active low input for enabling DIF pair 6. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

Active low input for enabling DIF pair 7. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

vOE6#

vOE7#

DIF_7

DIF_7#

GND

VDD

DIF_8

DIF_8#

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

PWR Ground pin.

PWR Power supply, nominal 3.3V

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

Active low input for enabling DIF pair 8. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

Active low input for enabling DIF pair 9. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

vOE8#

vOE9#

DIF_9

DIF_9#

VDD

GND

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

PWR Power supply, nominal 3.3V

PWR Ground pin.

DIF_10

DIF_10#

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

Active low input for enabling DIF pair 10. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

Active low input for enabling DIF pair 11. This pin has an internal pull-down

1 =disable outputs, 0 = enable outputs

vOE10#

vOE11#

DIF_11

DIF_11#

OUT 0.7V differential true clock output

OUT 0.7V differential Complementary clock output

IDT^®12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

1682D- 11/19/15

1 2 345 6 7...17

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