9FGU0631 DATASHEET
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
1
vSS_EN_tri
IN
IN
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
2
3
4
5
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
OUT
PWR
PWR
LATCHED
I/O
Power supply for XTAL, nominal 1.5V
VDD for REF output. nominal 1.5V.
6
vSADR/REF1.5
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
7
8
9
NC
GNDDIG
SCLK_3.3
N/A
GND
IN
I/O
PWR
PWR
No Connection.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.5V digital power (dirty power)
10 SDATA_3.3
11 VDDDIG1.5
12 VDDIO
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominally 1.5V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
No Connection.
13 vOE0#
IN
14 DIF0
15 DIF0#
16 VDD1.5
17 VDDIO
18 DIF1
19 DIF1#
20 NC
OUT
OUT
PWR
PWR
OUT
OUT
N/A
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
No Connection.
1.5V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominally 1.5V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
21 vOE1#
IN
22 DIF2
23 DIF2#
OUT
OUT
24 vOE2#
IN
25 NC
N/A
PWR
PWR
OUT
OUT
26 VDDA1.5
27 VDDIO
28 DIF3
29 DIF3#
30 vOE3#
IN
31 VDD1.5
32 VDDIO
33 DIF4
PWR
PWR
OUT
OUT
34 DIF4#
35 vOE4#
IN
36 DIF5
37 DIF5#
OUT
OUT
38 vOE5#
39 VDDIO
IN
PWR
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
40 ^CKPWRGD_PD#
41 ePAD
IN
GND
Connect paddle to ground.
OCTOBER 18, 2016
3
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