Datasheet > 9FGU0841AKLFT

9FGU0841AKLFT

更新时间： 2024-01-29 10:08:14

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
16页	207K
描述
8-output 1.5V PCIe Gen1-2-3 Clock Generator

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中文翻译

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数据手册

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9FGU0841AKLFT 数据手册

8-output 1.5V PCIe Gen1-2-3 Clock Generator

w/Zo=100ohms

9FGU0841

DATASHEET

General Description

Features/Benefits

The 9FGU0841 is a member of IDT's 1.5V Ultra-Low-Power

PCIe clock family with integrated output terminations

providing Zo=100Ω. The device has 8 output enables for clock

management, 2 different spread spectrum levels in addition to

spread off and 2 selectable SMBus addresses.

• Direct connection to 100ohm transmission lines; saves 32

resistors compared to standard PCIe devices

• 50mW typical power consumption; reduced thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05 and 1.5V; maximum power savings

Recommended Application

• 1.5V PCIe Gen1-2-3 Clock Generator

• OE# pins; support DIF power management

• Programmable Slew rate for each output; allows tuning for

various line length

• Programmable output amplitude; allows tuning for various

Output Features

• 8 - 100MHz Low-Power (LP) HCSL DIF pairs

w/Zo=100ohms

application environments

• DIF outputs blocked until PLL is locked; clean system

start-up

• 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)

support

• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;

reduces EM

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

Key Specification

• Configuration can be accomplished with strapping pins;

• DIF cycle-to-cycle jitter <50ps

SMBus interface not required for device control

• DIF output-to-output skew < 60ps

• DIF phase jitter is PCIe Gen1-2-3 compliant

• REF phase jitter is < 3.0ps RMS

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• 3.3V tolerant SMBus interface works with legacy controllers

• Space saving 48-pin 6x6 mm VFQFPN; minimal board

space

Functional Block Diagram

vOE(7:0)#

REF1.5

XIN/CLKIN_25

OSC

DIF7

DIF6

DIF5

SS Capable PLL

DIF4

DIF3

DIF2

DIF1

DIF0

vSADR

vSS_EN_tri

CONTROL

LOGIC

^CKPWRGD_PD#

SDATA_3.3

SCLK_3.3

9FGU0841 OCTOBER 18, 2016

12 3 4 5 6 7...16

中文翻译

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9FGV0231AKILF	IDT	获取价格	2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
9FGV0231AKILFT	IDT	获取价格	2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
9FGV0231AKLF	IDT	获取价格	2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
9FGV0231AKLFT	IDT	获取价格	2-OUTPUT VERY LOW POWER PCIE GEN1-2-3 CLOCK GENERATOR
9FGV0241	IDT	获取价格	2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR