9DBL0442 / 9DBL0452 DATASHEET
Pin Descriptions
Pin# Pin Name
Type
Pin Description
Tri-level input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2
(Bypass mode) with internal pull up/pull down resistors. See PLL Operating Mode Table for
Details.
LATCHED
IN
1
^vHIBW_BYPM_LOB
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
2
3
4
FB_DNC
FB_DNC#
VDDR3.3
DNC
DNC
PWR
5
6
7
8
9
CLK_IN
CLK_IN#
NC
GNDDIG
SCLK_3.3
IN
IN
N/A
GND
IN
True Input for differential reference clock.
Complementary Input for differential reference clock.
No Connection.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
10 SDATA_3.3
11 VDDDIG3.3
I/O
PWR
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
Active low input for enabling output 0. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
12 vOE0#
IN
13 DIF0
14 DIF0#
15 VDDO3.3
16 NC
OUT
OUT
PWR
N/A
Differential true clock output
Differential Complementary clock output
Power supply for outputs,nominal 3.3V.
No Connection.
17 DIF1
18 DIF1#
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 1. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
19 vOE1#
IN
20 NC
N/A
PWR
OUT
OUT
No Connection.
3.3V power for the PLL core.
Differential true clock output
Differential Complementary clock output
21 VDDA3.3
22 DIF2
23 DIF2#
Active low input for enabling output 2. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
24 vOE2#
IN
25 VDDO3.3
26 NC
PWR
N/A
Power supply for outputs,nominal 3.3V.
No Connection.
27 DIF3
28 DIF3#
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 3. This pin has an internal 120kohm pull-down.
1 =disable outputs, 0 = enable outputs
No Connection.
29 vOE3#
30 NC
IN
N/A
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal 120kohm pull-up resistor.
31 ^CKPWRGD_PD#
IN
LATCHED Tri-level latch to select SMBus Address. It has an internal 120kohm pull down resistor.
32 vSADR_tri
33 epad
IN
See SMBus Address Selection Table.
connect epad to ground.
GND
NOTE: DNC indicates Do Not Connect anything to this pin.
FEBRUARY 22, 2017
3
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
5秒后页面跳转
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