Datasheet > 9DBL0243ANLGI

9DBL0243ANLGI

更新时间： 2022-02-26 11:13:26

品牌	Logo	应用领域
艾迪悌 - IDT		瞄准线
页数	文件大小	规格书
22页	387K
描述
2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

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9DBL0243ANLGI 数据手册

9DBL0243 / 9DBL0253 Datasheet

Table 4. SMBus Parameters (Cont.)

Parameter

Symbol

Conditions

Minimum Typical

Maximum Units Notes

Nominal Bus Voltage

SCLK/SDATA Rise Time

SCLK/SDATA Fall Time

SMBus Operating Frequency

V_DDSMB

2.7

3.6

1000

300

t_RSMB(Max V_IL- 0.15V) to (Min V_IH+ 0.15V)

t_FSMB

f_SMB

(Min V_IH+ 0.15V) to (Max V_IL- 0.15V)

SMBus operating frequency

500

kHz

2,3

¹Guaranteed by design and characterization, not 100% tested in production.

²The device must be powered up for the SMBus to function.

³The differential input clock must be running for the SMBus to be active.

Table 5. Input/Supply/Common Parameters

Parameter

Symbol

Conditions

Minimum

Typical

Maximum Units Notes

Supply Voltage

VDDx

Supply voltage for core and analog

3.135

3.3

3.465

Ambient Operating

Temperature

T_AMB

V_IH

Industrial range

-40

°C

V_DDx

0.3

Input High Voltage

Single-ended inputs, except SMBus

0.75 V_DDx

Input Low Voltage

Input High Voltage

Input Mid Voltage

Input Low Voltage

V_IL

V_IHtri

V_IMtri

V_ILtri

I_IN

-0.3

0.25 V_DDx

V_DD+ 0.3

Single-ended tri-level inputs ('_tri' suffix)

0.75 V_DDx

0.4 V_DDx0.5 V_DDx0.6 V_DDx

-0.3

-5

0.25 V_DDx

Single-ended inputs, V_IN= GND, V_IN= V_DDx

Single-ended inputs

μA

_IN= 0 V; Inputs with internal pull-up

resistors

_IN= VDD; Inputs with internal pull-down

Input Current

I_INP

-50

μA

resistors

Bypass mode

PLL mode

200

160

MHz

Input Frequency

Pin Inductance

F_IN

100.00

L_pin

C_IN

Logic Inputs, except DIF_IN

1.5

Capacitance

C_{INDIF_IN}DIF_IN differential clock inputs

C_OUTOutput pin capacitance

2.7

CLK_IN Loss of

Signal Detect Time

t_LOS

4.2

CLK_IN Loss of

Signal Release

Time

t_LOSREL

t_STAB

0.12

0.5

1.8

Clk Stabilization

1,2

March 15, 2017

1 2 3 456 7 8...22

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