Datasheet > 9DBL0243ANLGI

9DBL0243ANLGI

更新时间： 2022-02-26 11:13:26

品牌	Logo	应用领域
艾迪悌 - IDT		瞄准线
页数	文件大小	规格书
22页	387K
描述
2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

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9DBL0243ANLGI 数据手册

9DBL0243 / 9DBL0253 Datasheet

Table 5. Input/Supply/Common Parameters (Cont.)

Parameter

Symbol

Conditions

Minimum

Typical

Maximum Units Notes

Input SS

Modulation

Frequency PCIe

Allowable frequency for PCIe applications

(Triangular Modulation)

f_MODINPCIe

31.5

kHz

Input SS

Modulation

Frequency

non-PCIe

Allowable frequency for non-PCIe

applications (Triangular Modulation)

f_MODIN

DIF start after OE# assertion

DIF stop after OE# deassertion

OE# Latency

Tdrive_PD#

t_LATOE#

t_DRVPD

clocks

1,3

DIF output enable after

PD# de-assertion

300

μs

Tfall

t_F

Fall time of single-ended control inputs

Rise time of single-ended control inputs

Trise

t_R

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are > 200mV.

Table 6. Clock Input Parameters

Parameter

Symbol

Conditions

Minimum

Typical

Maximum Units Notes

Input Crossover Voltage – DIF_IN V_CROSSCross over voltage

150

300

0.4

-5

900

V/ns

μA

Input Swing – DIF_IN

Input Slew Rate – DIF_IN

Input Leakage Current

V_SWINGDifferential value

dv/dt

I_IN

Measured differentially

1,2

V_IN= V_{DD ,}V_IN= GND

Measurement from differential

waveform

Input Duty Cycle

d_tin

Input Jitter –Cycle to Cycle

J_DIFInDifferential measurement

125

¹Guaranteed by design and characterization, not 100% tested in production.

²Slew rate measured through ±75mV window centered around differential zero.

March 15, 2017

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