Datasheet > 9DBL0243ANLGI

9DBL0243ANLGI

更新时间： 2022-02-26 11:13:26

品牌	Logo	应用领域
艾迪悌 - IDT		瞄准线
页数	文件大小	规格书
22页	387K
描述
2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

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9DBL0243ANLGI 数据手册

9DBL0243 / 9DBL0253 Datasheet

Table 7. DIF Low-Power HCSL Outputs

Parameter

Symbol

Conditions

Minimum

Typical Maximum Units Notes

Slew Rate

dV/dt

Scope averaging on, fast setting

Scope averaging on, slow setting

Slew rate matching

2.0

1.3

2.8

2.0

V/ns 1,2,3

2.9

Slew Rate Matching

Voltage High

ΔdV/dt

V_HIGH

1,2,4

Statistical measurement on

single-ended signal using

oscilloscope math function. (Scope

averaging on)

660

754

850

Voltage Low

V_LOW

-150

-3

150

Maximum Voltage

Minimum Voltage

Vmax

Vmin

Measurement on single ended signal

using absolute value. (Scope

averaging off)

797

-39

1150

-300

250

Crossing Voltage (abs) Vcross_abs

Crossing Voltage (var) Δ-Vcross

Scope averaging off

384

550

140

1,5

1,6

¹Guaranteed by design and characterization, not 100% tested in production.

²Measured from differential waveform.

³Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a ±50mV window around

differential 0V.

⁴Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the

average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

⁵Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge

(i.e. Clock rising and Clock# falling).

⁶The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)

allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.

⁷At default SMBus settings.

Table 8. Current Consumption

Parameter

Symbol

Conditions

Minimum

Typical

Maximum Units Notes

I_DDA

V_DDA, PLL Mode at 100MHz

V_DDDIG,PLL Mode at 100MHz

Operating Supply

Current

I_DDDIG

3.3

I_DDO+RV_DDO+ V_DDR, PLL Mode, all outputs at 100MHz

I_DDRPDV_DDA, CKPWRGD_PD# = 0

1.0

4.3

1.4

0.6

3.0

0.9

Power Down

Current

I_DDDIGPDV_DDDIG, CKPWRGD_PD# = 0

I_DDAOPDV_DDO+ V_DDR, CKPWRGD_PD# = 0

¹Input clock stopped.

March 15, 2017

1...4 5 678 9 10...22

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