Datasheet > 9DBL0243ANLGI

9DBL0243ANLGI

更新时间： 2022-02-26 11:13:26

品牌	Logo	应用领域
艾迪悌 - IDT		瞄准线
页数	文件大小	规格书
22页	387K
描述
2-Output 3.3V LP-HCSL Zero-Delay Buffer with LOS Indicator

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9DBL0243ANLGI 数据手册

9DBL0243 / 9DBL0253 Datasheet

Pin Assignments

Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View

24 23 22 21 20 19

FB_DNC 1

FB_DNC# 2

VDDR3.3 3

CLK_IN 4

DIF1#

DIF1

9DBL0243

9DBL0253

LOS

connect EPAD to

GND

VDDA3.3

CLK_IN# 5

GNDDIG 6

13 vOE0#

9 10 11 12

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

^v prefix indicates internal 120KOhm pull up AND pull down resistor

(biased to VDD/2)

v prefix indicates internal 120KOhm pull down resistor

Pin Descriptions

Table 1. Pin Descriptions

Number

Name

Type

Description

True clock of differential feedback. The feedback output and feedback input are

connected internally on this pin. Do not connect anything to this pin.

FB_DNC

DNC

Complement clock of differential feedback. The feedback output and feedback input

are connected internally on this pin. Do not connect anything to this pin.

FB_DNC#

VDDR3.3

DNC

Power supply for differential input clock (receiver). This V_DDshould be treated as an

analog power rail and filtered appropriately, nominally 3.3V.

Power

CLK_IN

CLK_IN#

Input

True input for differential reference clock.

Complementary input for differential reference clock.

GNDDIG

Ground Ground pin for digital circuitry.

SDATA_3.3

VDDDIG3.3

SCLK_3.3

VDDO3.3

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

Power 3.3V digital power (dirty power).

Input

Clock pin of SMBus circuitry, 3.3V tolerant.

Power Power supply for outputs, nominally 3.3V.

March 15, 2017

123 4 5 6 7...22

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