NXP Semiconductors
PN5180A0xx/C1/C2
High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes
VERSIONS. PRODUCTION TEST OF THIS FEATURE IS PERFORMED ON
PN5180A0HN/C3 AND PN5180A0ET/C3 ONLY.
• ACTIVE_MODE_TX_RF_ENABLE added to SYSTEM_CONFIG register
• The EMD block offers the possibility to stop and restart a CLIF Timer. This selection
can be done via register. The firmware 3.8 allows usage of any timer (T0, T1 or T2) as
CLIF timer.
• prepared for EMVCo. 2.6 digital compliancy
Version 3.9:
The DPC_XI can be configured in the RAM using SYSTEM_CONFIG, which is used
along with the AGC_XI in EEPROM for AGC correction. The DPC_XI in RAM can be
used using enable/disable bit in EEPROM. This allows to compensate a temperature
shift of the AGC to improve the accuracy of the DPC. (The temperature can be measured
externally by the host µC.)
• SYSTEM_CONFIG register bits in range[12-19] are used to configure the 8bit DPC_XI
value in RAM
• In EEPROM, Dynamic DPC_Xi RAM can be enabled/disabled using EEPROM
Misc_Config, bit 5
PN5180
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© NXP B.V. 2018. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 7 May 2018
240936
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