Datasheet > 935309309518

935309309518

更新时间： 2024-02-25 04:54:51

品牌	Logo	应用领域
恩智浦 - NXP		外围集成电路
页数	文件大小	规格书
108页	2288K
描述
Digital Signal Processor

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935309309518 技术参数

生命周期：	Active	Reach Compliance Code：	unknown
uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER	Base Number Matches：	1

935309309518 数据手册

DSP56303

Rev. 11, 2/2005

Freescale Semiconductor

Technical Data

DSP56303

24-Bit Digital Signal Processor

Memory Expansion Area

The DSP56303 is intended

for use in telecommunication

applications, such as multi-

line voice/data/ fax

Triple

Timer

X Data

RAM

Y Data

RAM

PrograM

RAM

HI08

ESSI

SCI

2048 × 24

4096 × 24

bits

(default)

processing, video

Peripheral

Expansion Area

conferencing, audio

applications, control, and

general digital signal

processing.

YAB

Address

External

XAB

PAB

DAB

Generation

Unit

Address

Bus

Address

Switch

Six-Channel

DMA Unit

External

Bus

24-Bit

Interface

and Inst.

Cache

Bootstrap

ROM

DSP56300

Core

Control

DDB

YDB

XDB

PDB

GDB

External

Data Bus

Switch

Internal

Data

Bus

What’s New?

Rev. 11 includes the following

changes:

Data

Switch

•

Adds lead-free packaging and

part numbers.

Power

EXTAL

XTAL

Management

Clock

Generator

Data ALU

Program

Interrupt

Controller

Program

Decode

Program

Address

Generator

→

24 × 24 56 56-bit MAC

Two 56-bit Accumulators

56-bit Barrel Shifter

JTAG

PLL

Controller

OnCE™

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

PINIT/NMI

Figure 1. DSP56303 Block Diagram

The DSP56303 is a member of the DSP56300 core family of programmable CMOS DSPs. Significant architectural

features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The

DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0–3.6 volts. The DSP56300 core family

offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power to enable

wireless, telecommunications, and multimedia products.

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