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935308747518

更新时间: 2024-01-05 11:34:10
品牌 Logo 应用领域
恩智浦 - NXP 电信电信集成电路
页数 文件大小 规格书
160页 1064K
描述
Telecom Circuit

935308747518 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:unknown风险等级:5.7
电信集成电路类型:TELECOM CIRCUITBase Number Matches:1

935308747518 数据手册

 浏览型号935308747518的Datasheet PDF文件第3页浏览型号935308747518的Datasheet PDF文件第4页浏览型号935308747518的Datasheet PDF文件第5页浏览型号935308747518的Datasheet PDF文件第7页浏览型号935308747518的Datasheet PDF文件第8页浏览型号935308747518的Datasheet PDF文件第9页 
NXP Semiconductors  
PN5180A0xx/C1/C2  
High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes  
6 Versions  
All firmware versions smaller or equal to Verrion 3.9 are covered by this document.  
Firmware versions larger than Version 3.9 are covered by a dedicated document.  
Available firmware versions:  
Version 3.4: Allows EMVCO 2.3.1 compliant EMD error handling  
Version information:  
EEPROM address 0x12: 0x04  
EEPROM address 0x13: 0x03  
Version 3.5: Allows EMVCO 2.5 compliant EMD error handling  
Version information:  
EEPROM address 0x12: 0x05  
EEPROM address 0x13: 0x03  
Changes of Version 3.5 compared to Version 3.4:  
The EMD_CONTROL register is updated to support EMVCo 2.5.  
Adaptive Waveform Control (AWC) implemented  
Version 3.6: Automatic Receiver Control added  
No silicon initialized with this firmware is available. Usage of this firmware requires an  
update by the user.  
Version information:  
EEPROM address 0x12: 0x06  
EEPROM address 0x13: 0x03  
Changes of Version 3.6 compared to Version 3.5:  
Accessible EEPROM top address is changed to 0xFE  
EEPROM functional assignment starting at address 0xD8  
EEPROM updates to support using GPO1 during LPCD card detect and GPIO2 during  
wake-up from standby  
Adaptive Receiver configuration (ARC) available: EEPROM table updates for receiver  
configuration  
Energy of external RF field can be used to operate an external system-power-on switch  
Version 3.7: Not released  
Version 3.8: Firmware version prepared for EMVCo 2.6  
Changes of Version 3.6 compared to Version 3.8:  
EEPROM configuration for PLL_DEFAULT_SETTING (address 0x1C) had been  
updated with timer options and persistent testbus configuration added  
LDO_OUT pin is available for output of regulated 3.3V, configuration options added  
to SYSTEM_CONFIG register; SYSTEM_STATUS register is extended by bit  
LDO_TVDD_OK. THIS FEATURE CAN BE ENABLED ON ALL PN5180 PRODUCT  
PN5180  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2018. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.6 — 7 May 2018  
240936  
6 / 160  
 

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