Datasheet > 935308613118

935308613118

更新时间： 2024-11-07 15:27:15

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
32页	837K
描述
Analog Circuit

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技术参数
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935308613118 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.57
模拟集成电路 - 其他类型：	ANALOG CIRCUIT	Base Number Matches：	1

935308613118 数据手册

TDA8035

High integrated and low power smart card interface

Rev. 3.1 — 30 June 2016

Product data sheet

1. General description

The TDA8035 is the cost efficient successor of the established integrated contact smart

card reader IC TDA8024. It offers a high level of security for the card by performing

current limitation, short-circuit detection, ESD protection as well as supply supervision.

The current consumption during the standby mode of the contact reader is very low as it

operates in the 3 V supply domain. The TDA8035 is therefore the ideal component for a

power efficient contact reader.

2. Features and benefits

2.1 Protection of the contact smart card

 Thermal and short-circuit protection on all card contacts

 V_CCregulation:

 5 V, 3 V, 1.8 V  5 % on 2 220 nF multilayer ceramic capacitors with low ESR

 Current spikes of 40 nA/s (V_CC= 5 V and 3 V) or 15 nA/s (V_CC= 1.8 V) up to

20 MHz, with controlled rise and fall times. Filtered overload detection is

approximately 120 mA.

 Automatic activation and deactivation sequences initiated by software or by hardware

in the event of a short-circuit, card take-off, overheating, falling V_REGV_DD(INTF),V_DDP

 Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)

 Supply supervisor for killing spikes during power on and off:

 threshold internally fixed

 externally by a resistor bridge

2.2 Easy integration into your contact reader

 SW compatible to TDA8024 and TDA8034

 5 V, 3 V, 1.8 V smart card supply

 DC-to-DC converter for V_CCgeneration separately powered from 2.7 V to 5.5 V supply

(V_DDPand GNDP)

 Very low power consumption in Deep Shutdown mode

 Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8)

 External clock input up to 26 MHz

 Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with

synchronous frequency changes of f_XTAL, fXTAL/2, fXTAL/4 or fXTAL/8

 Non-inverted control of pin RST using pin RSTIN

 Built-in debouncing on card presence contact

 Multiplexed status signal using pin OFFN

12 3 4 5 6 7...32

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