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9300DMQB PDF预览

9300DMQB

更新时间: 2024-09-18 19:57:19
品牌 Logo 应用领域
美国国家半导体 - NSC 输入元件输出元件逻辑集成电路
页数 文件大小 规格书
6页 154K
描述
IC 93 SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16, Shift Register

9300DMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:CERAMIC, DIP-16Reach Compliance Code:unknown
风险等级:5.88其他特性:COMPLEMENTARY SERIAL SHIFT RIGHT OUTPUT; J AND KBAR SERIAL INPUT
计数方向:RIGHT系列:93
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.43 mm负载电容(CL):15 pF
逻辑集成电路类型:PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup:30000000 Hz
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):86 mA
传播延迟(tpd):24 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm最小 fmax:30 MHz
Base Number Matches:1

9300DMQB 数据手册

 浏览型号9300DMQB的Datasheet PDF文件第2页浏览型号9300DMQB的Datasheet PDF文件第3页浏览型号9300DMQB的Datasheet PDF文件第4页浏览型号9300DMQB的Datasheet PDF文件第5页浏览型号9300DMQB的Datasheet PDF文件第6页 
June 1989  
9300/DM9300 4-Bit Parallel-Access Shift Register  
General Description  
The 9300 4-bit registers feature parallel inputs, parallel out-  
puts, JK serial inputs, shift/load control input, and a direct  
overriding clear. The registers have two modes of operation:  
These shift registers are fully compatible with most other  
TTL and DTL families. All inputs, including the clock, are  
buffered to lower the drive requirements to one normalized  
Series 54/74 load.  
parallel (broadside) load and shift (in direction Q toward  
A
Q ).  
D
Features  
Y
Parallel loading is accomplished by applying the four bits of  
data and taking the shift/load control input low. The data is  
loaded into the associated flip-flops, and appears at the out-  
puts after the positive transition of the clock input. During  
loading, serial data flow is inhibited.  
Fully buffered inputs  
Y
Direct overriding clear  
Y
Synchronous parallel load  
Y
Parallel inputs and outputs from each flip-flop  
Shifting is accomplished synchronously when the shift/load  
control input is high. Serial data for this mode is entered at  
the JK inputs. These inputs permit the first stage to perform  
as a JK, D or T-type flip-flop as shown in the function table.  
Y
Positive edge-triggered clocking  
Y
J and K inputs to first stage  
Y
Typical shift frequencyÐ39 MHz  
Connection Diagram  
Dual-In-Line Package  
Order Number 9300DMQB,  
9300FMQB or DM9300N  
See NS Package Number  
J16A, N16E or W16A  
TL/F/6600–1  
Function Table  
Inputs  
Outputs  
Shift/  
Load  
Serial  
Parallel  
Clear  
Clock  
Q
A
Q
Q
C
Q
Q
D
B
D
J
K
P0  
P1  
P2  
P3  
L
X
L
X
X
X
X
L
L
H
H
X
X
X
H
L
X
a
X
b
X
c
X
d
L
a
L
b
L
c
L
d
H
d
H
H
H
H
H
H
u
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Q
A0  
Q
Q
Q
Q
B0  
A0  
An  
An  
An  
C0  
Bn  
Bn  
Bn  
Bn  
D0  
Cn  
Cn  
Cn  
Bn  
D0  
Cn  
Cn  
Cn  
Cn  
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
u
u
u
u
A0  
L
H
H
L
Q
An  
e
e
e
e
H
L
High Level (Steady State)  
Low Level (Steady State)  
Don’t Care  
X
Transition from low-to-high level  
u
a, b, c, d,  
e
The level of steady state input at P0, P1, P2, or P3 respectively.  
e
The level of Q , Q , Q , or Q , respectively before the indicated steady state input conditions were established.  
A B C D  
Q
, Q , Q , Q  
B0 C0  
A0  
An  
D0  
e
Q
, Q , Q  
Bn  
The level of Q , Q , Q , respectively, before the most recent  
B
transition of the clock.  
u
Cn  
A
C
C
1995 National Semiconductor Corporation  
TL/F/6600  
RRD-B30M105/Printed in U. S. A.  

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