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9112AM-16LF-T PDF预览

9112AM-16LF-T

更新时间: 2024-09-27 19:42:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 119K
描述
PLL Based Clock Driver, 9112 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-8

9112AM-16LF-T 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.13
逻辑集成电路类型:PLL BASED CLOCK DRIVERBase Number Matches:1

9112AM-16LF-T 数据手册

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ICS9112A-16  
Integrated  
Circuit  
Systems, Inc.  
Low Skew Output Buffer  
General Description  
Features  
The ICS9112A-16 is a high performance, low skew, low  
jitter clock driver. It uses a phase lock loop (PLL)  
technologytoalign, inbothphaseandfrequency, theREF  
input with the CLKOUT signal. It is designed to distribute  
high speed clocks in PC systems operating at speeds  
from 25 to  
Zero input - output delay  
Frequency range 25 - 133 MHz (3.3V)  
High loop filter bandwidth ideal for Spread  
Spectrum applications.  
Less than 200 ps Jitter between outputs  
Skew controlled outputs  
Skew less than 250 ps between outputs  
Available in 8 pin 150 mil SOIC  
or 173 mil TSSOP package.  
3.3V 10ꢀ operation  
133 MHz.  
ICS9112A-16 is a zero delay buffer that provides  
synchronization between the input and output. The  
synchronization is established via CLKOUT feed back to  
theinputofthePLL. Sincetheskewbetweentheinputand  
outputislessthan+/-350pS, thepartactsasazerodelay  
buffer.  
The ICS9112A-16 comes in an eight pin 150 mil SOIC or  
173 milTSSOP package. It has five output clocks. In the  
absence of REF input, will be in the power down mode. In  
this mode, the PLL is turned off and the output buffers are  
pulled low. Power down mode provides the lowest power  
consumption for a standby condition.  
Block Diagram  
Pin Configuration  
8 pin SOIC,TSSOP  
1337K—08/03/07  

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