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9112YG-27 PDF预览

9112YG-27

更新时间: 2024-09-27 18:36:55
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 1439K
描述
Low Skew Clock Driver, 9112 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.173 INCH, MO-153, LEAD FREE, TSSOP-8

9112YG-27 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.31系列:9112
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.4 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
传播延迟(tpd):3.8 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:3 mm最小 fmax:140 MHz
Base Number Matches:1

9112YG-27 数据手册

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ICS9112-27  
Integrated  
Circuit  
Systems, Inc.  
Low Skew PCI / PCI-X Buffer  
General Description  
The ICS9112-27 isahighperformance, lowskew, lowjitter  
PCI / PCI-X clock driver. It is designed to distribute high  
speed signals in PCI / PCI-X applications operating at  
speeds from 0 to 140 MHz.  
Features  
Frequency range 0 - 140 MHz (3.3V)  
Less than 200 ps Jitter between outputs  
Skew controlled outputs < 100 ps  
Distribute one clock input to one bank of four  
outputs  
3.3V 10ꢀ operation  
Available in 8 pin TSSOP, and SOIC packages.  
The ICS9112-27 ischaracterizedforoperationfrom-40°C  
to 85°C for automotive and industrial applications.  
Block Diagram  
Pin Configuration  
LOGIC  
CONTROL  
CLK_IN  
OE  
1
2
3
4
8
7
6
5
CLK3  
CLK2  
VDD  
OE  
CLK0  
CLK1  
CLK2  
CLK3  
CLK0  
GND  
CLK1  
8 pin TSSOP & SOIC  
Functionality Table  
CLK_IN  
INPUTS  
OUTPUTS  
CLK(3:0)  
Tristate  
0
CLK_IN  
OE  
0
0
0
1
1
1
0
Tristate  
1
1
Pin Descriptions  
PIN NUMBER  
PIN NAME  
TYPE  
DESCRIPTION  
1
CLK_IN  
OE  
IN  
Input reference frequency.  
Output enable. When OE is low, it tristates the clock outputs  
2
IN  
3
4
5
6
7
8
CLK0  
GND  
CLK1  
VDD  
OUT  
PWR  
OUT  
PWR  
OUT  
OUT  
Buffered clock output  
Ground  
Buffered clock output  
Power supply for 3.3V  
Buffered clock output  
Buffered clock output  
CLK2  
CLK3  
0055G—04/26/05  

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