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8SLVP2108ANLGI8 PDF预览

8SLVP2108ANLGI8

更新时间: 2022-02-26 11:08:25
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
22页 847K
描述
Low Phase Noise, Dual 1-to-8, 3.3V, 2.5V LVPECL Output Fanout Buffer

8SLVP2108ANLGI8 数据手册

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Low Phase Noise, Dual 1-to-8, 3.3V,  
2.5V LVPECL Output Fanout Buffer  
8SLVP2108  
Datasheet  
General Description  
Features  
The 8SLVP2108 is a high-performance differential dual 1:8  
LVPECL fanout buffer. The device is designed for the fanout of  
high-frequency, very low additive phase-noise clock and data  
signals. The 8SLVP2108 is characterized to operate from a 3.3V or  
2.5V power supply. Guaranteed output-to-output and part-to-part  
skew characteristics make the 8SLVP2108 ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. Two independent buffers with eight low skew outputs  
each are available. The integrated bias voltage references enable  
easy interfacing of single-ended signals to the device inputs. The  
device is optimized for low power consumption and low additive  
phase noise.  
Two 1:8, low skew, low additive jitter LVPECL fanout buffers  
Two differential clock inputs  
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can  
accept the following differential input levels: LVDS, LVPECL,  
CML  
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can  
also accept single-ended LVCMOS levels. See Applications  
section Wiring the Differential Input Levels to Accept  
Single-ended Levels (Figure 1A and Figure 1B).  
Maximum input clock frequency: 2GHz  
Output bank skew: 15ps (typical)  
Propagation delay: 390ps (maximum)  
Low additive phase jitter, RMS: 54fs (maximum)  
(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)  
Full 3.3V and 2.5V supply voltage  
Maximum device current consumption (IEE): 143mA  
Available in Lead-free (RoHS 6), 48-Lead VFQFN package  
Supports case temperature 105°C operations  
-40°C to 85°C ambient operating temperature  
Block Diagram  
QA0  
nQA0  
QA1  
nQA1  
V
CC  
QA2  
nQA2  
PCLKA  
nPCLKA  
  
  
  
  
  
  
  
  
Pin Assignment  
36 35 34 33 32 31 30 29 28 27 26 25  
Voltage  
Reference  
VCC  
37  
38  
39  
40  
24 VCC  
VREFA  
QA7  
nQA4  
QA4  
QB3  
nQB3  
QB4  
23  
22  
nQA7  
QB0  
nQB0  
21 nQA3  
8SLVP2108  
nQB4  
20  
19  
18  
17  
16  
QA3  
nQA2  
QA2  
41  
42  
43  
44  
45  
46  
48-lead VFQFN  
7mm x 7mm x 0.8mm  
package body  
QB5  
nQB5  
QB1  
nQB1  
QB6  
nQB6  
QB7  
nQA1  
QA1  
NL Package  
Top View  
V
CC  
QB2  
15 nQA0  
nQB2  
PCLKB  
QA0  
14  
47  
48  
1
nQB7  
VCC  
13 VCC  
2 3 4 5 6 7 8 9 10 11 12  
nPCLKB  
  
  
  
  
  
  
  
  
Voltage  
Reference  
VREFB  
QB7  
nQB7  
©2016 Integrated Device Technology, Inc.  
1
Revision B, November 21, 2016  

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