Datasheet > 8SLVS1118

8SLVS1118

更新时间： 2024-01-22 22:21:09

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
24页	555K
描述
LVDS/ LVPECL Fanout Buffer

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中文翻译

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数据手册

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8SLVS1118 数据手册

1:18, Low Skew, Low Additive Jitter

LVDS/ LVPECL Fanout Buffer

8SLVS1118

Datasheet

Description

Features

The 8SLVS1118 is a high-performance, low-power, differential

1:18 output fanout buffer. This highly versatile device is designed

for the fanout of high-frequency, very low additive phase-noise

clock and data signals. Guaranteed output-to-output and

part-to-part skew characteristics make the 8SLVS1118 ideal for

clock distribution applications that demand well-defined

performance and repeatability.

▪ 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer

▪ Low power consumption

▪ Differential PCLK, nPCLK clock pair accepts the following

differential/single-ended input levels: LVDS, LVPECL, and

LVCMOS

▪ Maximum input clock frequency: 2GHz

▪ Propagation delay: 290ps (typical)

▪ Output skew: 40ps (typical)

The device is characterized to operate from a 2.5V or 3.3V power

supply. The integrated bias voltage references enable easy

interfacing AC-coupled signals to the device inputs.

▪ Low additive phase jitter, RMS: 39fs (typical),

Integration Range: 12kHz – 20MHz,

(f_REF 156.25MHz, V_PP 1V, V_DD 3.3V)

▪ Full 2.5V and 3.3V supply voltage modes

▪ Device current consumption: 180mA (typical) IEE for LVPECL

output mode, 400mA (typical) IDD for LVDS output mode

▪ 48-VFQFN, lead-free (RoHS 6) packaging

▪ Transistor count: 1762

▪ -40°C to +85°C ambient operating temperature

▪ Supports case temperature up to 105°C

Block Diagram

8SLV1118I

nQ0

nQ1

nQ2

51k

Pull-down

PCLK

nPCLK

Pull-up /

Pull-down

51k

Q17

nQ17

Voltage

Reference

VREF

Pull-down

SEL_LVDS

51k

July 17, 2017

12 3 4 5 6 7...24

中文翻译

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