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8P34S1102NLGI PDF预览

8P34S1102NLGI

更新时间: 2024-10-01 01:10:31
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 348K
描述
1:2 LVDS Output 1.8V Fanout Buffer

8P34S1102NLGI 数据手册

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IDT8P34S1102I  
Datasheet  
1:2 LVDS Output 1.8V Fanout Buffer  
Features  
Description  
The IDT8P34S1102I is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of high-frequency, very  
low additive phase-noise clock and data signals.  
Two low skew, low additive jitter LVDS output pairs  
One differential clock input pair  
Differential CLK, nCLK pairs can accept the following differential  
The IDT8P34S1102I is characterized to operate from a 1.8V power  
supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the IDT8P34S1102I ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. One differential input and two low skew outputs are  
available. The integrated bias voltage reference enables easy  
interfacing of single-ended signals to the differential device input. The  
device is optimized for low power consumption and low additive  
phase noise.  
input levels: LVDS, CML  
Maximum input clock frequency: 1.2GHz  
Output skew: 3ps (typical)  
Propagation delay: 400ps (maximum)  
Low additive phase jitter, RMS; fREF = 156.25MHz,  
12kHz- 20MHz: 42fs (typical)  
Maximum device current consumption (IEE): 48mA  
Full 1.8V supply voltage  
Lead-free (RoHS 6), 16-Lead VFQFN packaging  
-40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
V
DD  
12 11 10  
9
Q0  
CLK  
nQ0  
13  
8
V
nc  
REF  
nCLK  
Q1  
nQ1  
nc 14  
nc 15  
7 nCLK  
6 CLK  
16  
5
VDD  
GND  
1
2
3
4
VREF  
VREF  
IDT8P34S1102I  
16-lead VFQFN  
3mm x 3mm x 0.925mm package body  
1.7mm x 1.7mm ePad Size  
NL Package  
Top View  
©2017 Integrated Device Technology, Inc.  
1
September 20, 2017  

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