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8P34S1106 PDF预览

8P34S1106

更新时间: 2024-10-01 14:58:03
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
17页 1230K
描述
1:6 LVDS Output 1.8V Fanout Buffer

8P34S1106 数据手册

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8P34S1106I  
Datasheet  
1:6 LVDS Output 1.8V Fanout Buffer  
Description  
Features  
Six low skew, low additive jitter LVDS output pairs  
The 8P34S1106I is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of high-frequency,  
very low additive phase-noise clock and data signals. The  
8P34S1106I is characterized to operate from a 1.8V power  
supply.  
One differential clock input pair  
Differential CLK, nCLK pair can accept the following differential  
input levels: LVDS, CML  
Maximum input clock frequency: 1.2GHz (maximum)  
Output skew: 20ps (typical)  
Guaranteed output-to-output and part-to-part skew  
characteristics make the 8P34S1106I ideal for those clock  
distribution applications demanding well-defined performance  
and repeatability. One differential input and six low skew  
outputs are available. The integrated bias voltage reference  
enables easy interfacing of single-ended signals to the  
differential device input. The device is optimized for low power  
consumption and low additive phase jitter.  
Propagation delay: 290ps (typical)  
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,  
12kHz–20MHz: 39fs (typical)  
Full 1.8V supply voltage  
Lead-free (RoHS 6), 20-Lead VFQFN packaging  
-40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
Q0  
V
DD  
15 14 13 12 11  
nQ0  
16  
17  
18  
19  
20  
10  
9
Q3  
nQ3  
Q4  
nQ0  
Q0  
CLK  
Q1  
nCLK  
8
VREF  
nCLK  
CLK  
Top View  
nQ1  
7
nQ4  
VDD  
6
VREF  
Q2  
1
2
3
4
5
nQ2  
8P34S1106I  
20-VFQFPN  
Q3  
4 x 4 x 0.9 mm package body  
2.1 x 2.1 mm ePad Size  
NLG Package  
Top View  
©2015–2023 Renesas Electronics Corporation  
1
R31DS0030EU0500 February 6, 2023  

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