Dual 1:2 LVDS Output 1.8V / 2.5V
Fanout Buffer
8P34S2102
Datasheet
Description
Features
▪ Dual 1:2 low skew, low additive jitter LVDS fanout buffers
The 8P34S2102 is a high-performance, low-power, differential
dual 1:2 LVDS output, 1.8V/2.5V fanout buffer. The device
supports fail-safe operation and is designed for the fanout of
high-frequency, very low additive phase-noise clock and data
signals.
▪ Matched AC characteristics across both channels
▪ High isolation between channels
▪ Both differential CLKA, nCLKA and CLKB, nCLKB inputs
accept LVDS, LVPECL and single-ended LVCMOS levels
Two independent buffer channels are available. Each channel has
two low-skew outputs. High isolation between channels minimizes
noise coupling. AC characteristics such as propagation delay are
matched between channels. Guaranteed output-to-output and
part-to-part skew characteristics make the 8P34S2102 ideal for
those clock distribution applications demanding well-defined
performance and repeatability.
▪ Maximum input clock frequency: 2GHz
▪ Output amplitudes: 350mV, 500mV (selectable)
▪ Output bank skew: 8ps typical
▪ Output skew: 10ps typical
▪ Low additive phase jitter, RMS: 45fs typical
(fREF = 156.25MHz, 12kHz–20MHz)
▪ Full 1.8V and 2.5V supply voltage mode
▪ Low device current consumption (IDD):
• 76mA typical: 1.8V
The device is characterized to operate from a 1.8V or a 2.5V
power supply. The integrated bias voltage references enable easy
interfacing of AC-coupled signals to the device inputs.
• 80mA typical: 2.5V
▪ Lead-free (RoHS 6), 16-lead VFQFPN packaging
▪ -40°C to +85°C ambient operating temperature
▪ Supports case temperature up to +105°C
Block Diagram
VDD
51k
QA0
nQA0
CLKA
nCLKA
QA1
nQA1
51k
51k
Voltage
Reference
VREF
VDD
51k
51k
QB0
nQB0
CLKB
nCLKB
QB1
nQB1
VDD
51k
51k
51k
SELA
8P34S2102 transistor count: 293
©2016-2023 Renesas Electronics Corporation
1
March 20, 2023