5秒后页面跳转
8P34S1204 PDF预览

8P34S1204

更新时间: 2024-10-01 14:58:27
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
18页 1571K
描述
2:4 LVDS 1.8V / 2.5V Fanout Buffer for 1PPS and High-Speed Clocks

8P34S1204 数据手册

 浏览型号8P34S1204的Datasheet PDF文件第2页浏览型号8P34S1204的Datasheet PDF文件第3页浏览型号8P34S1204的Datasheet PDF文件第4页浏览型号8P34S1204的Datasheet PDF文件第5页浏览型号8P34S1204的Datasheet PDF文件第6页浏览型号8P34S1204的Datasheet PDF文件第7页 
2:4 LVDS 1.8V / 2.5V Fanout Buffer  
for 1PPS and High-Speed Clocks  
8P34S1204  
Datasheet  
Description  
Features  
The 8P34S1204 is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of 1PPS signals or  
high-frequency, very low additive phase-noise clock and data  
signals. The 8P34S1204 supports fail-safe operation and is  
characterized to operate from a 1.8V or 2.5V power supply.  
Four low skew, low additive jitter LVDS output pairs  
Two selectable, differential clock input pairs  
Differential CLK, nCLK pairs can accept the following  
differential input levels: LVDS, CML  
Maximum input clock frequency: 1.5GHz  
LVCMOS/LVTTL interface levels for the control input select  
Output skew: 10ps (typical)  
Guaranteed low output-to-output and part-to-part skew  
characteristics make the 8P34S1204 ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. Two selectable differential inputs and four low skew  
outputs are available. The integrated bias voltage reference  
enables easy interfacing of single-ended signals to the device  
inputs. The device is optimized for low power consumption and  
low additive phase noise.  
Propagation delay: 400ps (maximum)  
Low propagation delay variation across temperature for 1PPS  
applications  
Low additive phase jitter, RMS; fREF = 156.25MHz,  
10kHz–20MHz: 34fs (typical)  
Device current consumption (IDD):  
65mA typical: 1.8V  
75mA typical: 2.5V  
Full 1.8V or 2.5V supply voltage  
Lead-free (RoHS 6), 16-Lead VFQFPN package  
-40°C to +85°C ambient operating temperature  
Supports case temperature up to +105°C  
Supports PCI Express Gen 1-5  
Pin Assignment  
Block Diagram  
VDD  
12 11 10  
9
Pulldown  
Q0  
nQ0  
CLK0  
13  
14  
15  
16  
8
7
6
5
Q2  
nQ2  
Q3  
VREF  
nCLK0  
CLK0  
VDD  
Pullup/Pulldown  
nCLK0  
Q1  
nQ1  
0
1
fREF  
nQ3  
Q2  
nQ2  
VDD  
1
2
3
4
Pulldown  
CLK1  
Q3  
Pullup/Pulldown  
nCLK1  
nQ3  
8P34S1204  
16-VFQFPN  
3 x 3 x 0.9 mm package body  
1.7 x 1.7 mm ePad Size  
Pulldown  
SEL  
NLG Package  
Top View  
Voltage  
Reference  
VREF  
©2022 Renesas Electronics Corporation  
1
June 14, 2022  

与8P34S1204相关器件

型号 品牌 获取价格 描述 数据表
8P34S1208 RENESAS

获取价格

2:8 LVDS 1.8V / 2.5V Fanout Buffer for 1PPS and High-Speed Clocks
8P34S1212 RENESAS

获取价格

2:12 LVDS 1.8V / 2.5V Fanout Buffer for 1PPS and High-Speed Clocks
8P34S1212NLGI IDT

获取价格

1:12 LVDS Output 1.8V Fanout Buffer
8P34S1212NLGI8 IDT

获取价格

1:12 LVDS Output 1.8V Fanout Buffer
8P34S2102 IDT

获取价格

Dual 1:2 LVDS Output 1.8V Fanout Buffer
8P34S2102 RENESAS

获取价格

Dual 1:2 LVDS 1.8V / 2.5V Fanout Buffer for 1PPS and High-Speed Clocks
8P34S2102_17 IDT

获取价格

Dual 1:2 LVDS Output 1.8V Fanout
8P34S2102NLGI IDT

获取价格

Dual 1:2 LVDS Output 1.8V Fanout Buffer
8P34S2102NLGI/W IDT

获取价格

Dual 1:2 LVDS Output 1.8V Fanout Buffer
8P34S2102NLGI8 IDT

获取价格

Dual 1:2 LVDS Output 1.8V Fanout Buffer