IDT8P34S1212I
Datasheet
1:12 LVDS Output 1.8V Fanout Buffer
Description
Features
The IDT8P34S1212I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1212I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1212I ideal for those clock
distribution applications that demand well-defined performance and
repeatability.
• 12 low skew, low additive jitter LVDS output pairs
• Two selectable, differential clock input pairs
• Differential CLK0, CLK1 pairs can accept the following differential
input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz (maximum)
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 10ps (typical)
Two selectable differential inputs and 12 low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
• Propagation delay: 340ps (typical)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz- 20MHz: 41fs (typical)
• Maximum device current consumption (IDD): 227mA (maximum)
at 1.89V
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 40-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
Q0
nQ0
30 29 28 27 26 25 24 23 22 21
Q1
nQ1
31
32
33
34
20
19
18
17
V
V
DD
DD
Q8
nQ8
Q9
nQ3
Q3
IDT8P34S1212I
40-Lead VFQFN
Q2
nQ2
V
DD
nQ2
Q3
nQ3
6.0mm x 6.0mm x 0.90mm
package body
nQ9 35
16 Q2
CLK0
Q4
nQ4
36
37
38
39
40
15
14
13
12
11
Q10
nQ10
Q11
nQ1
Q1
4.65mm x 4.65mm ePad Size
NL Package
nCLK0
Q5
nQ5
nQ0
Q0
fREF
Top View
nQ11
Q6
V
V
V
DD
DD
DD
nQ6
1
2
3
4
5
6
7
8
9
10
CLK1
Q7
nQ7
nCLK1
Q8
nQ8
Q9
nQ9
SEL
Q10
nQ10
VREF
VREF
Q11
nQ11
©2017 Integrated Device Technology, Inc.
1
November 24, 2017