FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
SST89E/V516 / 58 / 54 / 52RD2 FlashFlex51 MCU
Preliminary Specifications
FEATURES:
•
8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
•
Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
•
•
•
Programmable Watchdog Timer (WDT)
Programmable Counter Array (PCA)
Four 8-bit I/O Ports (32 I/O Pins) and
One 4-bit Port
•
•
SST89E5xxRD2 Operation
– 0 to 40 MHz at 5V
•
•
•
•
Second DPTR register
Low EMI Mode (Inhibit ALE)
SPI Serial Interface
SST89V5xxRD2 Operation
– 0 to 33 MHz at 3V
•
•
1 KByte Internal RAM
Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
Dual Block SuperFlash EEPROM
– 8/16/32/64 KByte primary block +
8 KByte secondary block
(128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
•
•
•
TTL- and CMOS-Compatible Logic Levels
Brown-out Detection
Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
•
•
Temperature Ranges:
•
Support External Address Range up to 64
KByte of Program and Data Memory
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
•
•
•
Three High-Current Drive Ports (16 mA each)
Three 16-bit Timers/Counters
Packages Available
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
PRODUCT DESCRIPTION
The SST89E5xxRD2 and SST89V5xxRD2 are members
of the FlashFlex51 family of 8-bit microcontroller products
designed and manufactured with SST’s patented and pro-
prietary SuperFlash CMOS semiconductor process tech-
nology. The split-gate cell design and thick-oxide tunneling
injector offer significant cost and reliability benefits for SST’s
customers. The devices use the 8051 instruction set and
are pin-for-pin compatible with standard 8051 microcontrol-
ler devices.
In addition to the 16/24/40/72 KByte of EEPROM program
memory on-chip, the devices can address up to 64 KByte
of external program memory. In addition to 1024 x8 bits of
on-chip RAM, up to 64 KByte of external RAM can be
addressed.
The flash memory blocks can be programmed via a stan-
dard 87C5x OTP EPROM programmer fitted with a special
adapter and the firmware for SST’s devices. During power-
on reset, the devices can be configured as either a slave to
an external host for source code storage or a master to an
external host for an in-application programming (IAP) oper-
ation. The devices are designed to be programmed in-sys-
tem and in-application on the printed circuit board for
maximum flexibility. The devices are pre-programmed with
an example of the bootstrap loader in the memory, demon-
strating the initial user program code loading or subsequent
user code updating via the IAP operation. The sample
bootstrap loader is available for the user’s reference and
convenience only; SST does not guarantee its functionality
or usefulness. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
The devices come with 16/24/40/72 KByte of on-chip flash
EEPROM program memory which is partitioned into 2
independent program memory blocks. The primary Block 0
occupies 8/16/32/64 KByte of internal program memory
space and the secondary Block 1 occupies 8 KByte of
internal program memory space.
The 8-KByte secondary block can be mapped to the lowest
location of the 8/16/32/64 KByte address space; it can also
be hidden from the program counter and used as an inde-
pendent EEPROM-like data memory.
©2004 Silicon Storage Technology, Inc.
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71255-00-000
1
3/04
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