89HPES12N3A
Product Brief
12 Lane 3-Port
PCI Express® Switch
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Flexible Architecture with Numerous Configuration Options
Device Overview
The 89HPES12N3A, a 12 lane 3-port PCI Express® switch, is a
member of the IDT PRECISE™ family of PCI Express switching solu-
tions. The PES12N3A is a peripheral chip that performs PCI Express
Packet switching with a feature set optimized for high performance
applications such as servers and storage. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports or peer-to-peer switching between downstream ports.
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Automatic per port link width negotiation to x4, x2 or x1
Automatic lane reversal on all ports
Automatic polarity inversion on all lanes
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Ability to load device configuration from serial EEPROM
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Legacy Support
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PCI compatible INTx emulation
Bus locking
The 89HPES12N3A offers an enhanced architecture and feature set
in a package that is pin-compatible with the first generation
89HPES12N3 12-lane, 3-port PCIe switch.
Highly Integrated Solution
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Requires no external components
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Incorporates on-chip internal memory for packet buffering and
queueing
Features
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Integrates twelve 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
High Performance PCI Express Switch
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Twelve 2.5Gbps PCI Express lanes
Three switch ports
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Reliability, Availability, and Serviceability (RAS) Features
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Supports ECRC and Advanced Error Reporting
Upstream port configurable up to x4
Downstream ports configurable up to x4
Low-latency cut-through switch architecture
Support for Max Payload Sizes up to 2048 bytes
One virtual channel
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Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
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Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
Eight traffic classes
PCI Express Base Specification Revision 1.1 compliant
Block Diagram
3-Port Switch Core
Port
Arbitration
Scheduler
Scheduler
Route Table
Frame Buffer
Transaction Layer
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Data Link Layer
Multiplexer/Demultiplexer
Multiplexer/Demultiplexer
Multiplexer/Demultiplexer
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Phy
Phy
Phy
Logical Logical
Layer Layer
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Phy
Phy
Phy
Phy
Phy
Phy
Phy
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
Logical
Layer
Logical Logical
Logical
Layer
Layer
Layer
SerDes
SerDes
SerDes
SerDes SerDes
SerDes
SerDes SerDes
SerDes
SerDes
SerDes
SerDes
12 PCI Express Lanes
One x4 Upstream Port and Two x4 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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February 8, 2007
© 2007 Integrated Device Technology, Inc.