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89H12T3BG2ZABC8 PDF预览

89H12T3BG2ZABC8

更新时间: 2024-01-13 09:27:28
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
30页 723K
描述
Bus Controller, PBGA324

89H12T3BG2ZABC8 技术参数

是否Rohs认证: 不符合生命周期:Active
Reach Compliance Code:not_compliant风险等级:5.85
JESD-30 代码:S-PBGA-B324JESD-609代码:e0
湿度敏感等级:3端子数量:324
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA324,18X18,40封装形状:SQUARE
封装形式:GRID ARRAY电源:1,2.5,3.3 V
认证状态:Not Qualified子类别:Bus Controllers
最大压摆率:781 mA表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

89H12T3BG2ZABC8 数据手册

 浏览型号89H12T3BG2ZABC8的Datasheet PDF文件第2页浏览型号89H12T3BG2ZABC8的Datasheet PDF文件第3页浏览型号89H12T3BG2ZABC8的Datasheet PDF文件第4页浏览型号89H12T3BG2ZABC8的Datasheet PDF文件第5页浏览型号89H12T3BG2ZABC8的Datasheet PDF文件第6页浏览型号89H12T3BG2ZABC8的Datasheet PDF文件第7页 
89HPES12T3BG2  
Data Sheet  
12-Lane 3-Port  
Gen2 PCI Express® Switch  
®
Flexible Architecture with Numerous Configuration Options  
Device Overview  
Automatic per port link width negotiation to x4, x2 or x1  
Automatic lane reversal on all ports  
Automatic polarity inversion  
The 89HPES12T3BG2 is a member of IDT’s PRECISE™ family of  
PCI Express® switching solutions. The PES12T3BG2 is a 12-lane, 3-  
port Gen2 peripheral chip that performs PCI Express Base switching  
with a feature set optimized for high performance applications such as  
servers, storage, and communications/networking. It provides connec-  
tivity and switching functions between a PCI Express upstream port and  
two downstream ports and supports switching between downstream  
ports.  
Ability to load device configuration from serial EEPROM  
On-Die Temperature Sensor  
Range of 0 to 127.5 degrees Celsius  
Three programmable temperature thresholds with over and  
under temperature threshold alarms  
Automatic recording of maximum high or minimum low  
temperature  
Features  
High Performance PCI Express Switch  
Legacy Support  
Twelve 5 Gbps Gen2 PCI Express lanes  
Three switch ports  
PCI compatible INTx emulation  
Bus locking  
• One x4 upstream port  
• Two x4 downstream ports  
Highly Integrated Solution  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates twelve 5 Gbps embedded SerDes with 8b/10b  
encoder/decoder (no separate transceivers needed)  
Low latency cut-through switch architecture  
Support for Max Payload Size up to 2048 bytes  
One virtual channel  
Eight traffic classes  
PCI Express Base Specification Revision 2.0 compliant  
• Receive equalization (RxEQ)  
Block Diagram  
3-Port Switch Core / 12 PCI Express Lanes  
Port  
Frame Buffer  
Route Table  
Arbitration  
Scheduler  
Transaction Layer  
Transaction Layer  
Data Link Layer  
Transaction Layer  
Data Link Layer  
Data Link Layer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Multiplexer / Demultiplexer  
Phy  
Phy  
Phy  
Logical  
Layer  
Logical  
Layer  
Logical  
Layer  
SerDes  
SerDes  
SerDes  
(Port 2)  
(Port 0)  
(Port 4)  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 30  
July 1, 2009  
© 2009 Integrated Device Technology, Inc  
*Notice: The information in this document is subject to change without notice  

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