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Datasheet > 873991AYLF
873991AYLF PDF预览

873991AYLF

更新时间： 2024-09-30 01:14:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
18页 270K
描述
LVPECL-TO-LVPECL/ECL CLOCK GENERATOR

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中文翻译

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873991AYLF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TQFP
包装说明：LQFP-52针数：52
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.54
其他特性：ECL MODE: VCC= 0V WITH VEE = -3.465V TO -3.135V系列：873991
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G52
JESD-609代码：e3长度：10 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：3
功能数量：1反相输出次数：
端子数量：52实输出次数：14
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP52,.47SQ封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.25 ns座面最大高度：1.6 mm
子类别：Clock Drivers最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

873991AYLF 数据手册

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873991  
LOW VOLTAGE, LVCMOS/  
LVPECL-TO-LVPECL/ECL CLOCK GENERATOR  
FEATURES  
GENERAL DESCRIPTION  
• 14 differential LVPECL outputs  
The 873991 is a low voltage, low skew, 3.3V LVPECL  
or ECL Clock Generator . The 873991 has two selectable  
clock inputs. The PCLK, nPCLK pair can accept an LVPECL  
• Selectable differential LVPECL or TEST_CLK inputs  
input and the TEST_CLK pin can accept a LVCMOS or LVT- • PCLK, nPCLK can accept the following input levels:  
TL input. This device has a fully integrated PLL along with  
frequency configurable outputs.An external feedback input and  
output regenerates clocks with “zero delay”.  
LVPECL, CML, SSTL  
• TEST_CLK accepts the following input levels:  
LVCMOS, LVTTL  
The four independent banks of outputs each have their  
own output dividers, which allow the device to generate a  
multitude of different bank frequency ratios and output-to-  
input frequency ratios.The output frequency range is 25MHz to  
400MHz and the input frequency range is 6.25MHz to 125MHz.  
The PLL_SEL input can be used to bypass the PLL for test  
and system debug purposes. In bypass mode, the input clock  
is routed around the PLL and into the internal output dividers.  
• Input frequency range: 6.25MHz to 125MHz  
• Output frequency: 400MHz (maximum)  
• VCO range: 200MHz to 800MHz  
• Output skew: 250ps (maximum)  
• Cycle-to-cyle jitter: 50ps (typical)  
• LVPECL mode operating voltage supply range:  
V
CC = 3.135V to 3.465V, VEE = 0V  
The 873991 also has a SYNC output which can be used for  
system synchronization purposes.It monitors Bank A and Bank  
C outputs for coincident rising edges and signals a pulse per the  
timing diagrams in this data sheet.This feature is used primarily  
in applications where Bank A and Bank C are running at different  
frequencies, and is particularly useful when they are running at  
non-integer multiples of each other.  
• ECL mode operating voltage supply range:  
V
CC = 0V, VEE = -3.465V to -3.135V  
• 0°C to 70°C ambient operating temperature  
• Industrial temperature available upon request  
• Lead-Free package fully RoHS compliant  
• Use replacement part 873996AYLF  
Example Applications:  
1. Line Card Multiplier: Multiply 19.44MHz from a back-plane  
to 77.76MHz on the line card ASIC and Serdes.  
PIN ASSIGNMENT  
2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies  
from a reference clock to multiple processing units on an  
embedded system.  
52-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y package  
Top View  
873991  
www.idt.com  
REV. A 8/25/15  
1
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中文翻译

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873991AYLF 替代型号

型号 品牌 替代类型 描述 数据表
873991AYLFT IDT

完全替代

 LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
ICS873991AYLF IDT

功能相似

 PLL Based Clock Driver, 873991 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, 10
ICS873991AYLFT IDT

功能相似

 PLL Based Clock Driver, 873991 Series, 13 True Output(s), 0 Inverted Output(s), PQFP52, 10

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