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873996AY

更新时间： 2024-09-29 21:02:11
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
21页 352K
描述
Clock Driver

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中文翻译

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873996AY 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
Base Number Matches：1

873996AY 数据手册

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DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY/MULTIPLIER/DIVIDER  
ICS873996  
GENERAL DESCRIPTION  
FEATURES  
• Six differential 3.3V LVPECL outputs  
The ICS873996 is a Zero Delay/Multiplier/Divider  
ICS  
with hitless input clock switching capability and a  
member of the HiPerClockS™ family of low jitter/  
phase noise devices from IDT. The ICS873996 is  
ideal for use in redundant, fault tolerant clock trees  
• Selectable differential clock inputs  
HiPerClockS™  
• CLKx, nCLKx pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
where low phase noise and low jitter are critical. The device  
receives two differential LVPECL clock signals from which it  
generates 6 LVPECL clock outputs with “zero” delay. The output  
divider and feedback divider selections also allow for frequency  
multiplication or division.  
• Input clock frequency range: 49MHz to 213.33MHz  
• Output clock frequency range: 49MHz to 640MHz  
• VCO range: 490MHz to 640MHz  
• External feedback for “zero delay” clock regeneration  
with configurable frequencies  
The ICS873996 Dynamic Clock Switch (DCS) circuit  
continuously monitors both input clock signals. Upon detection  
of a failure (input clock stuck LOW or HIGH for at least 1 period),  
INP_BAD for that clock will be set HIGH. If that clock is the  
primary clock, the DCS will switch to the good secondary clock  
and phase/frequency alignment will occur with minimal output  
phase disturbance.  
• Output skew: 100ps (maximum)  
• RMS phase jitter (1.875MHz - 20MHz): 0.6ps (typical)  
assuming a low phase noise reference clock input  
• 3.3V supply voltage  
• 0°C to 70°C ambient operating temperature  
The low jitter characteristics combined with input clock monitor-  
ing and automatic switching from bad to good input clocks make  
the ICS873996 an ideal choice for mission critical applications  
that utilize 1G or 10G Ethernet or 1G/4G/10G Fibre Channel.  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
3
NA[2:0]  
nMR  
NA[2:0]  
PLL_SEL  
QA0  
nQA0  
CLK_INDICATOR  
INP1BAD  
INP0BAD  
nINIT  
Dynamic Switch  
Logic  
000 ÷1  
001 ÷2  
010 ÷3  
QA1  
nQA1  
011 ÷4  
100 ÷5  
48 47 46 45 44 43 42 41 40 39 38 37  
SEL_CLK  
101 ÷6  
1
QA2  
nQA2  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VCCO_A  
QA0  
PLL_SEL  
nMR  
110 ÷8  
111 ÷10(default)  
0
1
2
3
nQA0  
QA1  
nINIT  
ICS873996  
48-Lead TQFP, E-Pad  
7mm x 7mm x 1.0mm  
package body  
QB0  
nQB0  
MAN_OVERRIDE  
CLK0  
4
NB[2:0]  
VEE  
000 ÷1  
5
nQA1  
QA2  
CLK0  
0
1
001 ÷2  
nCLK0  
QB1  
nQB1  
010 ÷3  
6
nCLK0  
CLK1  
Phase  
Detector  
011 ÷4  
7
CLK1  
nCLK1  
100 ÷5  
nQA2  
VCCO_A  
VCCO_B  
QB0  
VCO  
490MHz - 640MHz  
101 ÷6  
QB2  
8
nCLK1  
EXT_FB  
nEXT_FB  
SEL_CLK  
BW  
110 ÷8  
Y Package  
Top View  
nQB2  
111 ÷10(default)  
9
NFB[2:0]  
10  
11  
12  
EXT_FB  
nEXT_FB  
nMR  
nMR  
000 Reserved  
nQB0  
QB1  
001 Reserved  
010 ÷3  
QFB  
011 ÷4  
BW  
nQFB  
13 14 15 16 17 18 19 20 21 22 23 24  
100 ÷5  
101 ÷6  
3
3
NB[2:0]  
110 ÷8  
111 ÷10(default)  
NFB[2:0]  
IDT™ / ICS™ 3.3V LVPECLZERO DELAY/MULTIPLIER/DIVIDER  
1
ICS873996AY REV. A FEBRUARY 19, 2008  
1234567...21

中文翻译

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