Datasheet > 873995

873995

更新时间： 2024-09-30 01:14:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	313K
描述
Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider

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873995 数据手册

Differential-to-3.3V LVPECL

Zero Delay/Multiplier/Divider

873995

DATA SHEET

GENERAL DESCRIPTION

FEATURES

• Six differential 3.3V LVPECL outputs

• Selectable differential clock inputs

The 873995 is a Zero Delay/Multiplier/Divider with hitless input clock

switching capability and a member of the family of low jitter/phase

noise devices from IDT. The 873995 is ideal for use in redundant,

fault tolerant clock trees where low phase noise and low jitter are

critical. The device receives two differential LVPECL clock signals

from which it generates 6 LVPECL clock outputs with “zero” delay.

The out-put divider and feedback divider selections also allow for

frequency multiplication or division.

• CLKx, nCLKx pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Input clock frequency range: 49MHz to 213.33MHz

• Output clock frequency range: 49MHz to 640MHz

• VCO range: 490MHz to 640MHz

The 873995 Dynamic Clock Switch (DCS) circuit continuously

monitors both input clock signals. Upon detection of a failure (input

clock stuck LOW or HIGH for at least 1 period), INP_BAD for that

clock will be set HIGH.If that clock is the primary clock, the DCS will

switch to the good secondary clock and phase/frequency alignment

will occur with minimal output phase disturbance.

• External feedback for “zero delay” clock regeneration

with conﬁgurable frequencies

• Output skew: 100ps (maximum)

• RMS phase jitter (1.875MHz - 20MHz): 0.77ps (typical) assum-

ing a low phase noise reference clock input

The low jitter characteristics combined with input clock monitoring

and automatic switching from bad to good input clocks make the

873995 an ideal choice for mission criti-cal applications that utilize

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• Use replacement part 873996AYLF

1G or 10G Ethernet or 1G/4G/10G Fibre Channel.

BLOCK DIAGRAM

PIN ASSIGNMENT

873995 REVISION A 8/25/15

12 3 4 5 6 7...20

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与873995相关器件

型号	品牌	获取价格	描述	数据表
873995AY	IDT	获取价格	Clock Driver, 873995 Series, 6 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 M
873995AYLF	IDT	获取价格	Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
873995AYLFT	IDT	获取价格	Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
873995AYT	IDT	获取价格	Clock Driver, 873995 Series, 6 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 M
873996	IDT	获取价格	Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
873996AY	IDT	获取价格	Clock Driver
873996AYLF	IDT	获取价格	Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
873996AYLFT	IDT	获取价格	Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider
873996AYT	IDT	获取价格	Clock Driver
873-IF190.0M-E	OSCILENT	获取价格	Base Station & Repeater