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8737AG-11 PDF预览

8737AG-11

更新时间: 2024-11-11 15:27:03
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 389K
描述
Low Skew Clock Driver, 8737 Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20

8737AG-11 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.13
系列:8737输入调节:DIFFERENTIAL MUX
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:20
实输出次数:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:1.7 ns传播延迟(tpd):1.7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.06 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:650 MHz
Base Number Matches:1

8737AG-11 数据手册

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ICS8737-11  
LOW SKEW, ÷1/÷2  
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS8737-11 is a low skew, high performance 2 divide by 1 differential 3.3V LVPECL outputs;  
Differential-to-3.3V LVPECL Clock Generator/Divider. The  
ICS8737-11 has two selectable clock inputs. The CLK, nCLK  
pair can accept most standard differential input levels. The  
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL  
input levels.The clock enable isinternally synchronized to  
eliminate runt pulses on theoutputs during asynchronous  
assertion/deassertion of the clock enable pin.  
2 divide by 2 differential 3.3V LVPECL outputs  
Selectable differential CLK, nCLK or LVPECL clock inputs  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
Guaranteed output and part-to-part skew characteristics  
make the ICS8737-11 ideal for clock distribution applications  
demanding well defined performance and repeatability.  
Maximum output frequency: 650MHz  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVPECL levels with resistor bias on nCLK input  
Output skew: 60ps (maximum)  
Part-to-part skew: 200ps (maximum)  
Bank skew: Bank A - 20ps (maximum),  
Bank B - 35ps (maximum)  
Additive phase jitter, RMS: 0.04ps (typical)  
Propagation delay: 1.7ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Lead-Free package RoHS compliant  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
QA0  
nQA0  
VEE  
CLK_EN  
CLK_SEL  
CLK  
nCLK  
PCLK  
nPCLK  
nc  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
QA0  
nQA0  
VCC  
QA1  
nQA1  
QB0  
nQB0  
VCC  
D
CLK_EN  
QA1  
nQA1  
Q
LE  
CLK  
nCLK  
PCLK  
÷1  
÷2  
0
1
nPCLK  
MR  
VCC  
9
10  
QB1  
nQB1  
QB0  
nQB0  
CLK_SEL  
MR  
ICS8737-11  
QB1  
nQB1  
20-Lead TSSOP  
6.50mm x 4.40mm x 0.92 package body  
G Package  
Top View  
8737AG-11  
www.idt.com  
REV. C AUGUST 9, 2010  
1

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