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8737AG-11LF PDF预览

8737AG-11LF

更新时间: 2024-11-12 01:16:59
品牌 Logo 应用领域
艾迪悌 - IDT PC驱动光电二极管逻辑集成电路
页数 文件大小 规格书
17页 228K
描述
Low Skew Differential-to-3.3V LVPECL Clock Generator

8737AG-11LF 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Lifetime Buy零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.36
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:11129361Samacsys Pin Count:20
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:PGG20Samacsys Released Date:2020-01-21 11:42:43
Is Samacsys:N系列:8737
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:20实输出次数:4
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:1.7 ns
传播延迟(tpd):1.7 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.06 ns座面最大高度:1.2 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
最小 fmax:650 MHzBase Number Matches:1

8737AG-11LF 数据手册

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Low Skew, ÷1/÷2 Differential-to-3.3V  
LVPECL Clock Generator  
8737-11  
DATASHEET  
GENERAL DESCRIPTION  
FEATURES  
The 8737-11 is a low skew, high performance 2 divide by 1 differential 3.3V LVPECL outputs;  
Differential-to-3.3V LVPECL Clock Generator/Divider. The  
8737-11 has two selectable clock inputs. The CLK, nCLK  
pair can accept most standard differential input levels. The  
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL  
input levels.The clock enable isinternally synchronized to  
eliminate runt pulses on theoutputs during asynchronous as-  
sertion/deassertion of the clock enable pin.  
2 divide by 2 differential 3.3V LVPECL outputs  
Selectable differential CLK, nCLK or LVPECL clock inputs  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
PCLK, nPCLK supports the following input types:  
LVPECL, CML, SSTL  
Guaranteed output and part-to-part skew characteristics make  
the 8737-11 ideal for clock distribution applications demanding  
well defined performance and repeatability.  
Maximum output frequency: 650MHz  
Translates any single ended input signal (LVCMOS, LVTTL,  
GTL) to LVPECL levels with resistor bias on nCLK input  
Output skew: 60ps (maximum)  
Part-to-part skew: 200ps (maximum)  
Bank skew: Bank A - 20ps (maximum),  
Bank B - 35ps (maximum)  
Additive phase jitter, RMS: 0.04ps (typical)  
Propagation delay: 1.7ns (maximum)  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Lead-Free package RoHS compliant  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
QA0  
nQA0  
VCC  
QA1  
nQA1  
QB0  
nQB0  
VCC  
VEE  
CLK_EN  
CLK_SEL  
CLK  
nCLK  
PCLK  
nPCLK  
nc  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
QB1  
nQB1  
MR  
VCC  
8737-11  
20-Lead TSSOP  
6.50mm x 4.40mm x 0.92 package body  
G Package  
Top View  
8737-11 REVISION C 2/13/15  
1
©2015 Integrated Device Technology, Inc.  

8737AG-11LF 替代型号

型号 品牌 替代类型 描述 数据表
8737AGI-11LFT IDT

完全替代

Low Skew Differential-to- 3.3V LVPECL Clock Generator
8737AGI-11LF IDT

完全替代

Low Skew Differential-to- 3.3V LVPECL Clock Generator
8737AG-11LFT IDT

完全替代

Low Skew Differential-to-3.3V LVPECL Clock Generator

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