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8701AY-01LF PDF预览

8701AY-01LF

更新时间: 2024-11-16 21:03:31
品牌 Logo 应用领域
艾迪悌 - IDT 驱动输出元件逻辑集成电路
页数 文件大小 规格书
11页 113K
描述
TQFP-48, Tray

8701AY-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.27
其他特性:SELECTABLE INVERTING AND NON-INVERTING OUTPUTS系列:8701
输入调节:STANDARDJESD-30 代码:S-PQFP-G48
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:5
端子数量:48实输出次数:15
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
Prop。Delay @ Nom-Sup:3.5 ns传播延迟(tpd):3.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.3 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

8701AY-01LF 数据手册

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Low Skew, ÷1, ÷2 LVCMOS/ LVTTL  
Clock Generator w/PolarIity Control  
ICS8701-01  
GENERAL DESCRIPTION  
ICS  
FEATURES  
The ICS8701-01 is a low skew, ÷1, ÷2 LVCMOS/  
LVTTL Clock Generator. The low impedance  
LVCMOS outputs are designed to drive 50Ω series  
or parallel terminated transmission lines. The effec-  
tive fanout can be increased from 20 to 40 by utilizing  
Twenty LVCMOS/LVTTL outputs, 7Ω typical output impedance  
• One LVCMOS/LVTTL clock input  
HiPerClockS™  
• Maximum output frequency: 250MHz  
• Selectable inverting and non-inverting outputs  
the ability of the outputs to drive two series terminated lines.  
• Bank enable logic allows unused banks to be  
disabled in reduced fanout applications  
The divide select inputs, DIV_SELx, control the output frequency  
of each bank. The outputs can be utilized in the ÷1, ÷2 or a combi-  
nation of ÷1 and ÷2 modes. The master reset/output enable input,  
nMR/OE, resets the internal dividers and controls the active and  
high impedance states of all outputs. The output polarity inputs,  
INV0:1, control the polarity (inverting or non-inverting) of the out-  
puts of each bank. Outputs QA0:QA4 are inverting for every com-  
bination of the INV0:1 input. The timing relationship between the  
inverting and non-inverting outputs at different frequencies is  
shown in the Timing Diagrams.  
• Output skew: 300ps (maximum)  
• Part-to-part skew: 700ps (maximum)  
• Bank skew: 250ps (maximum)  
• Multiple frequency skew: 350ps (maximum)  
• 3.3V or mixed 3.3V input, 2.5V output operating supply  
• 0°C to 70°C ambient operating temperature  
The ICS8701-01 is characterized at 3.3V and mixed 3.3V input  
supply, and 2.5V output supply operating modes. Guaranteed  
bank, output and part-to-part skew characteristics make the  
ICS8701-01 ideal for those clock distribution applications demand-  
ing well defined performance and repeatability.  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
÷1  
1
CLK  
QA0:QA4  
QB0:QB4  
QC0:QC4  
QD0:QD4  
÷2  
0
48 47 46 45 44 43 42 41 40 39 38 37  
DIV_SELA  
DIV_SELB  
DIV_SELC  
QC3  
VDDOC  
QC4  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QB1  
VDDOB  
QB0  
QA4  
VDDOA  
QA3  
GND  
QA2  
GND  
QA1  
VDDOA  
QA0  
1
0
2
3
QD0  
4
VDDOD  
QD1  
5
6
1
0
ICS8701-01  
GND  
QD2  
7
8
GND  
QD3  
9
10  
11  
12  
1
0
VDDOD  
QD4  
13 14 15 16 17 18 19 20 21 22 23 24  
DIV_SELD  
nMR/OE  
Output  
Polarity  
Control  
INV0  
INV1  
48-Pin LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
ICS8701AY-01 REVISION E MARCH 2, 2010  
1
©2010 Integrated Device Technology, Inc.  

8701AY-01LF 替代型号

型号 品牌 替代类型 描述 数据表
ICS8701AY-01LF IDT

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