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8701CYIT PDF预览

8701CYIT

更新时间: 2024-11-16 19:36:03
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
14页 224K
描述
Low Skew Clock Driver, 8701 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48

8701CYIT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.58系列:8701
输入调节:STANDARDJESD-30 代码:S-PQFP-G48
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH传播延迟(tpd):3.7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:7 mmBase Number Matches:1

8701CYIT 数据手册

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ICS8701I  
LOW SKEW, ÷1, ÷2  
CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS8701I is a low skew, ÷1, ÷2 Clock Generator. The  
low impedance LVCMOS outputs are designed to drive 50Ω  
series or parallel terminated transmission lines. The  
effective fanout can be increased from 20 to 40 by utilizing  
the ability of the outputs to drive two series terminated lines.  
Twenty LVCMOS outputs, 7Ω typical output impedance  
LVCMOS / LVTTL clock input  
• Maximum input frequency: 250MHz  
• Bank enable logic allows unused banks to be disabled  
in reduced fanout applications  
The divide select inputs, DIV_SELx, control the output  
frequency of each bank.The outputs can be utilized in the ÷1,  
÷2 or a combination of ÷1 and ÷2 modes. The bank enable  
inputs, BANK_EN0:1, support enabling and disabling each  
bank of outputs individually.The master reset input, nMR/OE,  
resets the internal frequency dividers and also controls the  
active and high impedance states of all outputs.  
• Bank skew: 200ps  
• Output skew: 250ps  
• Multiple frequency skew: 300ps  
• Part-to-part skew: 600ps  
The ICS8701I is characterized at 3.3V and mixed 3.3V input  
supply, and 2.5V output supply operating modes. Guaranteed  
bank, output and part-to-part skew characteristics make the  
ICS8701I ideal for those clock distribution applications de-  
manding well defined performance and repeatability.  
• 3.3V or mixed 3.3V input, 2.5V output operating supply  
• -40°C to 85°C ambient operating temperature  
• Other divide values available on request  
• Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
÷1  
CLK  
QA0:QA4  
0
÷2  
48 47 46 45 44 43 42 41 40 39 38 37  
DIV_SELA  
DIV_SELB  
DIV_SELC  
DIV_SELD  
QC3  
VDDO  
QC4  
QD0  
VDDO  
QD1  
GND  
QD2  
GND  
QD3  
VDDO  
QD4  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QB1  
VDDO  
QB0  
QA4  
VDDO  
QA3  
GND  
QA2  
GND  
QA1  
VDDO  
QA0  
1
0
2
QB0:QB4  
QC0:QC4  
QD0:QD4  
3
4
5
6
1
0
ICS8701I  
7
8
9
10  
11  
12  
1
0
13 14 15 16 17 18 19 20 21 22 23 24  
nMR/OE  
BANK_EN0  
BANK_EN1  
Bank Enable  
Logic  
48-Pin LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8701CYI  
www.idt.com  
REV.C JULY 27, 2010  
1

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