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8701AYI-01LF PDF预览

8701AYI-01LF

更新时间: 2024-09-29 20:37:31
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
10页 112K
描述
Clock Driver, 5V Series, 5 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-32

8701AYI-01LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.17
系列:5V输入调节:MUX
JESD-30 代码:S-PQFP-G48JESD-609代码:e3
长度:7 mm逻辑集成电路类型:CLOCK DRIVER
湿度敏感等级:3功能数量:4
反相输出次数:端子数量:48
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
Prop。Delay @ Nom-Sup:3.5 ns传播延迟(tpd):3.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.3 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mm最小 fmax:250 MHz
Base Number Matches:1

8701AYI-01LF 数据手册

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Low Skew, ÷1, ÷2 LVCMOS/ LVTTL  
Clock Generator w/PolarIity Control  
ICS8701I-01  
GENERAL DESCRIPTION  
ICS  
FEATURES  
The ICS8701I-01 is a low skew, ÷1, ÷2 LVCMOS/  
LVTTL Clock Generator.The low impedance LVCMOS  
outputs are designed to drive 50Ω series or parallel  
terminated transmission lines. The effective fanout  
can be increased from 20 to 40 by utilizing the ability  
Twenty LVCMOS/LVTTL outputs, 7Ω typical output impedance  
• One LVCMOS/LVTTL clock input  
HiPerClockS™  
• Maximum output frequency: 250MHz  
• Selectable inverting and non-inverting outputs  
of the outputs to drive two series terminated lines.  
• Bank enable logic allows unused banks to be  
disabled in reduced fanout applications  
The divide select inputs, DIV_SELx, control the output frequency  
of each bank.The outputs can be utilized in the ÷1, ÷2 or a combi-  
nation of ÷1 and ÷2 modes. The master reset/output enable input,  
nMR/OE, resets the internal dividers and controls the active and  
high impedance states of all outputs. The output polarity inputs,  
INV0:1, control the polarity (inverting or non-inverting) of the out-  
puts of each bank. Outputs QA0:QA4 are inverting for every com-  
bination of the INV0:1 input. The timing relationship between the  
inverting and non-inverting outputs at different frequencies is  
shown in the Timing Diagrams.  
• Output skew: 300ps (maximum)  
• Part-to-part skew: 700ps (maximum)  
• Bank skew: 250ps (maximum)  
• Multiple frequency skew: 350ps (maximum)  
• 3.3V or mixed 3.3V input, 2.5V output operating supply  
• -40°C to 85°C ambient operating temperature  
The ICS8701I-01 is characterized at 3.3V and mixed 3.3V input  
supply, and 2.5V output supply operating modes. Guaranteed  
bank, output and part-to-part skew characteristics make the  
ICS8701I-01 ideal for those clock distribution applications de-  
manding well defined performance and repeatability.  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
1
0
÷1  
÷2  
CLK  
QA0:QA4  
QB0:QB4  
QC0:QC4  
QD0:QD4  
48 47 46 45 44 43 42 41 40 39 38  
DIV_SELA  
QC3  
VDDOC  
QC4  
1
2
3
4
5
6
7
8
9
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
QB1  
37  
1
0
VDDOB  
QB0  
QD0  
QA4  
DIV_SELB  
DIV_SELC  
VDDOD  
QD1  
VDDOA  
QA3  
1
0
ICS8701I-01  
GND  
QD2  
GND  
QA2  
GND  
QD3  
GND  
QA1  
10  
11  
12  
1
0
VDDOD  
QD4  
VDDOA  
QA0  
13 14 15 16 17 18 19 20 21 22  
23 24  
DIV_SELD  
nMR/OE  
Output  
Polarity  
Control  
INV0  
INV1  
48-Pin LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
ICS8701AYI-01 REVISION A MARCH 2, 2010  
1
©2010 Integrated Device Technology, Inc.  

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