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87016AYLF PDF预览

87016AYLF

更新时间: 2024-11-10 01:13:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 271K
描述
Low Skew LVCMOS/LVTTL Clock Generator

87016AYLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Lifetime Buy零件包装代码:TQFP
包装说明:LQFP-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.01
系列:87016输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N16JESD-609代码:e3
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:16
实输出次数:16最高工作温度:85 °C
最低工作温度:输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HQCCN
封装等效代码:QFP48,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.5 ns
传播延迟(tpd):4.5 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.17 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:OTHER
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:250 MHzBase Number Matches:1

87016AYLF 数据手册

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Low Skew, 1-to-16  
LVCMOS/LVTTL Clock Generator  
87016  
DATASHEET  
GENERAL DESCRIPTION  
FEATURES  
The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)  
The device has 4 banks of 4 outputs and each bank can be  
• Selectable differential CLK1, nCLK1 or  
independently selected for ÷1 or ÷2 frequency operation. Each  
LVCMOS clock input  
bank also has its own power supply pins so that the banks can  
operate at the following different voltage levels: 3.3V, 2.5V, and  
1.8V.The low impedance LVCMOS/LVTTL outputs are designed  
to drive 50Ω series or parallel terminated transmission lines.  
CLK1, nCLK1 pair can accept the following differential input  
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• CLK0 supports the following input types:  
LVCMOS, LVTTL  
The divide select inputs, DIV_SELA:DIV_SELD, control the  
output frequency of each bank. The output banks can be  
independently selected for ÷1 or ÷2 operation.The bank enable  
inputs, CLK_ENA:CLK_END, support enabling and disabling  
each bank of outputs individually. The CLK_ENA:CLK_END  
circuitry has a synchronizer to prevent runt pulses when  
enabling or disabling the clock outputs. The master reset  
input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the  
active and high impedance states of all outputs. This pin has  
an internal pull-up resistor and is normally used only for test  
purposes or in systems which use low power modes.  
• Maximum output frequency: 250MHz  
• Independent bank control for ÷1 or ÷2 operation  
• Independent output bank voltage settings for 3.3V, 2.5V,  
or 1.8V operation  
• Asynchronous clock enable/disable  
• Output skew: 170ps (maximum)  
• Bank skew: 30ps (maximum)  
The 87016 is characterized to operate with the core at  
3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed  
bank, output, and part-to-part skew characteristics make  
the 87016 ideal for those clock applications demanding  
well-defined performance and repeatability.  
• Part-to-part skew: 750ps (maximum)  
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply  
• 0°C to 85°C ambient operating temperature  
• Available in lead-free RoHS compliant package  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
48-Pin LQFP  
7mm x 7mm x 1.4mm body package  
Y Package  
Top View  
.
87016 REVISION C 06/26/15  
1
©2015 Integrated Device Technology, Inc.  

87016AYLF 替代型号

型号 品牌 替代类型 描述 数据表
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完全替代

Low Skew LVCMOS/LVTTL Clock Generator

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