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87016AYT

更新时间： 2024-01-05 05:56:20
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 197K
描述
Low Skew Clock Driver, 87016 Series, 16 True Output(s), 0 Inverted Output(s), CMOS, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48

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87016AYT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.03
系列：87016输入调节：DIFFERENTIAL
JESD-30 代码：S-XQCC-N16JESD-609代码：e0
长度：7 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：16
实输出次数：16最高工作温度：85 °C
最低工作温度：输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：HQCCN
封装等效代码：QFP48,.35SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG峰值回流温度（摄氏度）：240
电源：1.8/3.3,3.3 V传播延迟（tpd）：4.5 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.17 ns
座面最大高度：1.6 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Lead (Sn85Pb15)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：7 mm
最小 fmax：250 MHzBase Number Matches：1

87016AYT 数据手册

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ICS87016  
LOW SKEW, 1-TO-16  
LVCMOS/LVTTL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS87016 is a low skew, 1:16 LVCMOS/LVTTL Clock • Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)  
Generator. The device has 4 banks of 4 outputs and each  
• Selectable differential CLK1, nCLK1 or  
bank can be independently selected for ÷1 or ÷2 frequency  
LVCMOS clock input  
operation. Each bank also has its own power supply pins so  
that the banks can operate at the following different voltage  
levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/  
LVTTL outputs are designed to drive 50Ω series or parallel  
terminated transmission lines.  
• CLK1, nCLK1 pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
• CLK0 supports the following input types:  
LVCMOS, LVTTL  
The divide select inputs, DIV_SELA:DIV_SELD, control the  
output frequency of each bank. The output banks can be  
independently selected for ÷1 or ÷2 operation.The bank enable  
inputs, CLK_ENA:CLK_END, support enabling and disabling  
each bank of outputs individually. The CLK_ENA:CLK_END  
circuitry has a synchronizer to prevent runt pulses when  
enabling or disabling the clock outputs. The master reset  
input, nMR/OE, resets the ÷1/÷2 flip flops and also controls the  
active and high impedance states of all outputs. This pin has  
an internal pull-up resistor and is normally used only for test  
purposes or in systems which use low power modes.  
• Maximum output frequency: 250MHz  
• Independent bank control for ÷1 or ÷2 operation  
• Independent output bank voltage settings for 3.3V, 2.5V,  
or 1.8V operation  
• Asynchronous clock enable/disable  
• Output skew: 170ps (maximum)  
• Bank skew: 30ps (maximum)  
• Part-to-part skew: 750ps (maximum)  
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply  
• 0°C to 85°C ambient operating temperature  
The ICS87016 is characterized to operate with the core at  
3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed bank,  
output, and part-to-part skew characteristics make the  
87016 ideal for those clock applications demanding  
well-defined performance and repeatability.  
• Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
nMR/OE  
PIN ASSIGNMENT  
D
CLK0  
4
4
4
1
0
LE  
÷1  
÷2  
QA0:QA3  
0
1
48 47 46 45 44 43 42 41 40 39 38 37  
VDD  
CLK0  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
GND  
QB0  
CLK1  
2
nCLK1  
D
DIV_SELA  
DIV_SELB  
DIV_SELC  
DIV_SELD  
CLK_ENA  
CLK_ENB  
CLK_ENC  
CLK_END  
nMR/OE  
3
VDDOB  
QB1  
LE  
1
0
QB0:QB3  
QC0:QC3  
CLK_SEL  
4
5
GND  
QB2  
6
DIV_SELA  
DIV_SELB  
D
ICS87016  
7
VDDOB  
QB3  
LE  
1
0
8
9
GND  
QC0  
VDDOC  
QC1  
DIV_SELC  
DIV_SELD  
10  
11  
12  
D
4
LE  
1
0
QD0:QD3  
GND  
13 14 15 16 17 18 19 20 21 22 23 24  
CLK_ENA  
CLK_ENB  
CLK_ENC  
CLK_END  
48-Pin LQFP  
7mm x 7mm x 1.4mm body package  
Y Package  
Top View  
ICS87016AY  
REVISION B APRIL 4, 2013  
1
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