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8634BK-01T PDF预览

8634BK-01T

更新时间: 2024-11-11 20:40:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
17页 284K
描述
PLL Based Clock Driver, 8634 Series, 5 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.95 MM HEIGHT, MO-220, VFQFN-32

8634BK-01T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:5 X 5 MM, 0.95 MM HEIGHT, MO-220, VFQFN-32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.9
系列:8634输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-XQCC-N32JESD-609代码:e0
长度:5 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:32
实输出次数:5最高工作温度:70 °C
最低工作温度:封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC32,.2SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225电源:3.3 V
Prop。Delay @ Nom-Sup:4.2 ns传播延迟(tpd):4.2 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.025 ns
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:5 mm最小 fmax:700 MHz
Base Number Matches:1

8634BK-01T 数据手册

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ICS8634-01  
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL  
ZERO DELAY BUFFER  
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES 4/25/2015  
GENERAL DESCRIPTION  
FEATURES  
The ICS8634-01 is a high performance 1-to-5 Differen-  
tial-to-3.3V LVPECL Zero Delay Buffer. The ICS8634-01 has  
two selectable clock inputs. The CLKx, nCLKx pair can accept  
most standard differential input levels. Utilizing one of the out-  
puts as feedback to the PLL, output frequencies up to 700MHz  
can be regenerated with zero delay with respect to the input.  
Dual reference clock inputs support redundant clock or multiple  
reference applications.  
Five differential 3.3V LVPECL outputs  
Selectable differential clock inputs  
CLKx, nCLKx pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL  
Output frequency range: 31.25MHz to 700MHz  
Input frequency range: 31.25MHz to 700MHz  
VCO range: 250MHz to 700MHz  
External feedback for “zero delay” clock regeneration  
Cycle-to-cycle jitter: 25ps (maximum)  
Output skew: 25ps (maximum)  
PLL reference zero delay: 50ps 100ps  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Lead-Free package available  
Industrial temperature information available upon request  
Functional replacement parts; 8735AY-31LF,  
8735BYI-01LF or 8735BKI-01LF  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
Q0  
nQ0  
PLL_SEL  
Q1  
nQ1  
÷4, ÷8  
0
1
32 31 30 29 28 27 26 25  
CLK0  
nCLK0  
0
1
Q2  
nQ2  
1
2
3
4
5
6
7
24  
23  
22  
21  
20  
19  
18  
SEL0  
SEL1  
VCCO  
Q3  
CLK1  
nCLK1  
Q3  
nQ3  
CLK0  
nQ3  
Q2  
PLL  
nCLK0  
CLK1  
Q4  
nQ4  
CLK_SEL  
ICS8634-01  
nQ2  
Q1  
nCLK1  
CLK_SEL  
FB_IN  
nFB_IN  
nQ1  
VCCO  
8
17  
MR  
9
10 11 12 13 14 15 16  
SEL0  
SEL1  
MR  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
Top View  
32-Lead VFQFN  
5mm x 5mm x 0.95 package body  
K Package  
Top View  
8634BY-01  
1
www.idt.com  
REV. D MAY 12, 2014  

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