Datasheet > 854S202AYIT

854S202AYIT

更新时间： 2024-01-01 04:02:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	371K
描述
Clock Driver

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854S202AYIT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Base Number Matches：	1

854S202AYIT 数据手册

ICS854S202I

12:2, DIFFERENTIAL-LVDS MULTIPLEXER

PRELIMINARY

TABLE 4D. LVDS DC CHARACTERISTICS, V_DD= 3.3V 5ꢀ, TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

410

Maximum Units

V_OD

Differential Output Voltage

Δ V_OD

V_OS

V_ODMagnitude Change

Offset Voltage

1.3

Δ V_OS

V_OSMagnitude Change

NOTE: Please refer to Parameter Measurement Information for output information.

TABLE 5. AC CHARACTERISTICS, V_DD= 3.3V 5ꢀ, TA = -40°C TO 85°C

Symbol

Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

GHz

Propagation Delay, Low to High;

NOTE 1

Propagation Delay, High to Low;

NOTE 1

tp_LH

tp_HL

660

tsk(o)

tsk(i)

Output Skew; NOTE 2, 3

Input Skew; NOTE 3

TBD

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section,

NOTE 5

155.52MHz,

Integration Range:

12kHz - 20MHz

tjit

0.16

t_R/ t_F

odc

Output Rise/Fall Time

Output Duty Cycle

20ꢀ to 80ꢀ

110

ꢀ

MUX_ISOLATIONMUX Isolation

f_OUT< 1.2GHz

All parameters measured at 500MHz, unless noted otherwise.

NOTE 1: Measured from V_DD/2 of the input to V_DD/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DD/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and

with equal load conditions. Using the same type of input on each device, the output is measured at V_DD/2.

NOTE 5: Driving only one input clock.

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS854S202AYI REV. A JANUARY 26, 2007

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