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854S015CKI-01LFT PDF预览

854S015CKI-01LFT

更新时间: 2024-02-07 10:02:13
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
27页 940K
描述
Low Skew, 1-to-5, Differential-to-LVDS/LVPECL Fanout Buffer

854S015CKI-01LFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN, LCC24,.16SQ,20针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.46
Samacsys Description:VFQFP-N 4MM X 4MM X 0.9 MM MM- NO LEAD系列:854S
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-XQCC-N24
JESD-609代码:e3长度:4 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3 VProp。Delay @ Nom-Sup:0.8 ns
传播延迟(tpd):0.8 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.055 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:4 mm
最小 fmax:2000 MHzBase Number Matches:1

854S015CKI-01LFT 数据手册

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Low Skew, 1-to-5,  
Differential-to-LVDS/LVPECL Fanout Buffer  
ICS854S015I-01  
DATA SHEET  
General Description  
Features  
The ICS854S015I-01 is a low skew, high performance 1-to-5, 2.5V,  
3.3V Differential-to-LVPECL/LVDS Fanout Buffer. The  
ICS854S015I-01 has two selectable differential clock inputs.  
Five differential LVPECL or LVDS output pairs  
Two differential clock input pairs  
CLK, nCLK pair can accept the following differential input levels:  
Guaranteed output and part-to-part skew characteristics make the  
ICS854S015I-01 ideal for those applications demanding well defined  
performance and repeatability.  
LVDS, LVPECL, LVHSTL, HCSL  
PCLK, nPCLK can accept the following input levels: LVPECL,  
LVDS, CML  
Either CLK or PCLK inputs can be configured to accept  
single-ended inputs  
Maximum output frequency: 2GHz  
Additive phase jitter, RMS: 0.065ps (maximum), 3.3V,  
156.25MHz, 12kHz – 5MHz)  
Output Skew: 55ps (maximum)  
Propagation delay: 570ps (typical) @ 3.3V  
Full 3.3V or 2.5V supply modes  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Block Diagram  
Pin Assignment  
Pulldown  
nCLK_EN  
D
Q
LE  
Pulldown  
PCLK  
nPCLK  
24 23 22 21 20 19  
0
1
Pullup/Pulldown  
PCLK  
1
2
3
4
5
6
nQ1  
VCC  
18  
Q0  
nQ0  
17  
Pulldown  
nPCLK  
VCC  
CLK  
nCLK  
Pullup/Pulldown  
Q1  
16 VEE  
15 Q2  
nQ1  
VCC_TAP  
CLK  
Pulldown  
CLK_SEL  
VCC_TAP  
Q2  
nQ2  
14  
nQ2  
13 Q3  
nCLK  
7
8
9 10 11 12  
Q3  
nQ3  
Q4  
nQ4  
ICS854S015I-01  
24-Lead VFQFN  
Pulldown  
SEL_OUT  
4mm x 4mm x 0.925mm package body  
K Package  
Top View  
ICS854S015CKI-01 REVISION A OCTOBER 4, 2011  
1
©2011 Integrated Device Technology, Inc.  

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