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853S12AKI PDF预览

853S12AKI

更新时间: 2024-01-03 01:28:05
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
16页 396K
描述
Low Skew Clock Driver, 853S Series, 12 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32

853S12AKI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN,针数:32
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.33其他特性:ALSO OPERATES AT 3.3V SUPPLY
系列:853S输入调节:DIFFERENTIAL
JESD-30 代码:S-XQCC-N32JESD-609代码:e0
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:32实输出次数:12
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:1 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:5 mm
Base Number Matches:1

853S12AKI 数据手册

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ICS853S12I  
LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER  
PRELIMINARY  
LVPECL CLOCK INPUT INTERFACE  
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 2A to 2F show interface  
examples for the HiPerClockS PCLK/nPCLK input driven by  
the most common driver types. The input interfaces suggested  
here are examples only. If the driver is from another vendor,  
use their termination recommendation. Please consult with the  
vendor of the driver component to confirm the driver termination  
requirements.  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
Zo = 50 Ohm  
R1  
50  
R2  
50  
CML  
Zo = 50 Ohm  
Zo = 50 Ohm  
PCLK  
PCLK  
R1  
100  
nPCLK  
nPCLK  
Zo = 50 Ohm  
HiPerClockS  
HiPerClockS  
PCLK/nPCLK  
PCLK/nPCLK  
CML Built-In Pullup  
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY AN OPEN COLLECTOR CML DRIVER  
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A BUILT-IN PULLUP CML DRIVER  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
125  
R4  
125  
R3  
84  
R4  
84  
C1  
C2  
Zo = 50 Ohm  
Zo = 50 Ohm  
3.3V LVPECL  
Zo = 50 Ohm  
Zo = 50 Ohm  
PCLK  
PCLK  
nPCLK  
HiPerClockS  
PCLK/nPCLK  
nPCLK  
HiPerClockS  
Input  
LVPECL  
R5  
100 - 200  
R6  
100 - 200  
R1  
125  
R2  
125  
R1  
84  
R2  
84  
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A 3.3V LVPECL DRIVER  
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A 3.3V LVPECL DRIVER WITH AC COUPLE  
3.3V  
2.5V  
3.3V  
3.3V  
3.3V  
2.5V  
Zo = 50 Ohm  
R3  
1K  
R4  
1K  
R3  
R4  
120  
120  
C1  
C2  
LVDS  
SSTL  
Zo = 60 Ohm  
Zo = 60 Ohm  
PCLK  
PCLK  
R5  
100  
nPCLK  
nPCLK  
Zo = 50 Ohm  
HiPerClockS  
PCLK/nPCLK  
HiPerClockS  
PCLK/nPCLK  
R1  
1K  
R2  
1K  
R1  
120  
R2  
120  
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY AN SSTL DRIVER  
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN  
BY A 3.3V LVDS DRIVER  
IDT/ ICSLVPECL FANOUT BUFFER  
8
ICS853S12AKI REV. A MARCH 29, 2007  

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