Datasheet > 853S12AKI

853S12AKI

更新时间： 2024-01-21 11:06:24

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
16页	396K
描述
Low Skew Clock Driver, 853S Series, 12 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32

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853S12AKI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.33	其他特性：	ALSO OPERATES AT 3.3V SUPPLY
系列：	853S	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e0
长度：	5 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	12
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
座面最大高度：	1 mm	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	5 mm
Base Number Matches：	1

853S12AKI 数据手册

ICS853S12I

LOW SKEW, 1-TO-12, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER

PRELIMINARY

ADDITIVE PHASE JITTER

band to the power in the fundamental. When the required offset

is specified, the phase noise is called a dBc value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications.Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz

Additive Phase Jitter

622MHz (12kHz to 20MHz) = 0.05ps typical

OFFSET FROM CARRIER FREQUENCY (HZ)

As with most timing specifications, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise floor of the equipment is higher than

the noise floor of the device. This is illustrated above. The device

meets the noise floor of what is shown, but can actually be lower.

The phase noise is dependant on the input source and

measurement equipment.

IDT^™/ ICS^™LVPECL FANOUT BUFFER

ICS853S12AKI REV. A MARCH 29, 2007

1 2 3 456 7 8...16

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与853S12AKI相关器件

型号	品牌	描述	获取价格	数据表
853S12AKIT	IDT	Low Skew Clock Driver, 853S Series, 12 True Output(s), 0 Inverted Output(s), 5 MM X 5 MM,	获取价格
853S12I	RENESAS	Low Skew,1-to-12,Differential-to-3.3V,2.5V LVPECL Fanout Buffer	获取价格
853S202AYI	IDT	Clock Driver	获取价格
853S202I	RENESAS	12:2 Differential-to-LVPECL Clock Multiplexer	获取价格
853S314AFI	IDT	Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 M	获取价格
853S314AFILF	IDT	Low Skew Clock Driver, 853S Series, 4 True Output(s), 0 Inverted Output(s), PDSO20, 5.30 M	获取价格

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